This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm². The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm². The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

Key words: Signal processing; Drowsiness detection; Wavelet transform; Best m-term approximation; Frequency bands; DB2 Wavelet

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm². For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digitalto-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular-VTH transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step.