This paper presents an instrumentation amplifier for ECG signals, compared with the traditional three op amp ECG read instrumentation amplifier, the circuit overcomes the disadvantage of low common mode rejection ratio due to resistance mismatch of the three operational amplifier. At the same time, the circuit uses the inverting integral amplifier as an DC offset feedback circuit to eliminate the offset voltage at the input of the amplifier. This circuit implements the class-AB control circuit to achieve high linearity output. The circuit is compact with few peripheral components. The circuit is designed and implemented by using 0.18 um CMOS Technology. The circuit test results show that the circuit can eliminate the input offset voltage of the 140 mv. And has a DC gain of 40 dB and a common mode rejection ratio (CMRR) of 120 dB at the 2 V supply voltage. THD is −64 dB, and the total input reference noise is 0.78 µVrms, the power consumption is 121.6 µW, the bandwidth is 2 kHz.

This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0–388 pF. The proposed CDC was realized using 0.18 μm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 μA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%–90% RH.

An accuracy-improved and internal regulator-free temperature on-chip sensor is proposed. The proposed sensor outputs an accuracy-enhanced pulse width modulation (PWM) signal with a nonlinear current mode feedback pseudo-PLL(Phase-Locked Loop). The pseudo-PLL is able to greatly mitigate the nonlinearity caused by process parameters (eg. threshold voltage and mobility of MOS transistor) without careful compensation. Furthermore, to optimize the area and power supply rejection without an internal regulator, a current mode input and feedback approach in the pseudo-PLL is also presented. The proposed sensor is fabricated with 0.18μm standard CMOS process. The measurement results show that the power consumption of the sensor is only 2μW under 1.2V supply voltage. With the supply voltage varying within 1 1.2V, the temperature detection error is maintained within +/-0.2∘C in the range of -20∘C to 100∘C. And the corresponding power supply rejection (PSR) ratio and resolution achieve about 0.15∘C/100mV and 0.12∘C, respectively.

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions.

We present a simple ripple-transferring replica pseudo PLL loop technique for a highly digital ADC. The ADC is mainly constituted by main and replica pseudo PLL loops. Compared with the conventional techniques, the technique minimizes the main loop’s input ripple by means of inverting the replica loop’s input ripple and transferring it to the input of the main loop for the sum of the two ripples, so the accuracy of the ADC should be improved. To achieve the transfer function above, on the transferring path, a wide-band current mode amplifier is proposed. The proposed ADC is well suited for accuracy and power improved design. Fabricated with a 0.18μm CMOS process, the ADC achieves 65dB SNDR while operating from a 1.2V supply and using a 1kHz input sine wave. Moreover, the power dissipation is only 11μW.

This paper presents an implantable pressure sensor readout system (IPRO) which can work at low voltage and does not need internal low dropout regulator (LDO). This paper has made a series of optimizations for power consumption. The power supply of IPRO uses 434 MHz energy harvesting (EH), which only uses two-stage rectification and is equipped with corresponding ultra-low power undervoltage locking (UVLO) circuit. The analog front-end (AFE) and signal processing parts use current mode and differential pseudo phase locked loop (DPPLL), which can work stably under low voltage and maintain a certain degree of accuracy and power rejection ability. The wireless data transmission part adopts the impulse ultra-wide band (IR-UWB) scheme. Its ultra-low power consumption allows it to be powered by a charge pump, which is the first time it has been proposed in implantable systems. In order to further optimize power consumption, a simplest encoding circuit suitable for the front-end output form was proposed, and a power oscillator (PO) with accelerated start-up was used to optimize area and power consumption. The system is implemented in 180 nm Complementary Metal Oxide Semiconductor (CMOS) process, with a chip area of 1.1 * 1.0 mm ² . The measurement results indicate that the typical working voltage of the IPRO is 0.8 V, the typical power consumption is 11.8 μW, and the accuracy is 1.11 mmHg. Compared with existing designs, there is a significant optimization in supply voltage and power consumption.