This article presents a dynamic range (DR) enhanced discrete-time delta–sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5-bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital-to-analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold ( $V_{\text {TH}}$ ) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7-dB DR and 92.4-dB signal-to-noise-and-distortion ratio (SNDR) at a 700-Hz bandwidth with only 2.3- $\mu \text{W}$ power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.

This study proposes a low-power delta-sigma capacitance-to-digital converter (CDC) for a capacitive sensor. The input of the capacitive sensor employs a zoom-in technique with the offset capacitor to extend the input capacitance range. The proposed CDC uses a third-order switched capacitor delta-sigma modulator to provide a digital output, based on a cascade of integrators with a feed forward (CIFF) structure. The current-starved operational transconductance amplifiers (OTAs) are applied in the delta-sigma modulator’s first integrator to improve current efficiency and reduce power consumption. An auto-zeroing technique is used in the OTAs to reduce their offset and noise. The circuit was implemented in a 0.18 μm CMOS technology and occupies an area of 0.496 mm2. The measurable capacitance range of the CDC can be varied from 0 pF to 8 pF. In a measurement time of 0.8 ms, the delta-sigma CDC achieved a 12.7 effective number of bits while consuming 18.6 μA current from a 2 V supply voltage.

This paper presents a low power, energy-efficient precision CMOS temperature sensor. The front-end circuit is based on bipolar junction transistors, and employs a pre-bias circuit and bipolar core. To reduce measurement errors arising from current ratio mismatch, a new dynamic element-matching mode is proposed, which dynamically matches all current sources in the front-end circuit. The first-order fitting and third-order fitting are used to calibrate the output results. On the basis of simulation results, the sensor achieves 3σ-inaccuracies of +0.18/−0.13 °C from −55 °C to +125 °C. Measurement results demonstrate sensor 3σ-inaccuracies of ±0.2 °C from 0 °C to +100 °C. The circuit is implemented in 0.18 μm CMOS, and consumes 6.1 μA with a 1.8 V supply voltage.

This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma (ΔΣ) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH ΔΣ ADC were evaluated. The proposed ADC is fabricated and measured in a 180 nm CMOS process, achieving a DR, peak SNDR, and SFDR of 100.2 dB, 98.5 dB, and 116.7 dB, respectively, within a 2.56 kHz bandwidth, consuming only 20.1 μW. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR are 179.6 dB and 181.3 dB, respectively. The measurement results of the prototype 3-0 MASH ΔΣ ADC closely matched the theoretical predictions. This consistency between the measurements and the theoretical analysis confirms the reliability of the design approach in achieving the expected performance.

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.