We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau-Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.

We report on the impact of process variations on short-channel negative capacitance (NC)-based FinFETs through statistical Monte Carlo simulations using a physics-based model of NC-FinFETs. We find that relative to regular FinFETs, the impact of geometrical variability can be lesser or higher in NC-FinFETs in different regimes of device operation and is strongly dependent on the nominal ferroelectric (FE) thickness (t _fe ). The contribution of the FE layer to the overall variability behaves non-monotonically with increase in the nominal t _fe . While the OFF-current and threshold voltage variabilities scale down, the ON-current variability does not follow a monotonic trend with increase in the nominal t _fe . We also show that although relative to the regular FinFET-based ring oscillator (RO) circuit, the NC-FinFET-based RO (NC-RO) circuit displays increased immunity to process variation induced delay variability, the trend is non-monotonic with regard to t _fe scaling.

We have developed a physics based model for negative capacitance (NC) FinFETs by coupling the Landau-Khalatnikov model of ferroelctric materials with the standard BSIM-CMG model of FinFET. We apply our model to thin film Y-HfO₂ (yttrium-doped hafnium oxide) based NC-FinFETs designed using state of the art 22nm technology node FinFETs. Using the same ferroelectric material, we demonstrate a device design that can match the I_ON of the 22nm technology node at 50% reduced V_DD with a simultaneous I_OFF improvement of ≈ 83%. Further, we analyze the impact of variation of ferroelectric properties, remnant polarization (P_r) and coercive electric field (E_c) on the device figures of merit which can lay a very useful guideline towards investigation of new ferroelectric materials for NC-FinFET. We investigate the impact of scaling the ferroelectric thickness on the electrical characteristics of NC-FinFET. We critically examine an interesting phenomenon of “negative DIBL” which leads to reduced off-current (I_OFF), increased threshold voltage (V_th), yet increased on-current (I_ON) at higher drain biases. This effect gets pronounced with increasing ferroelectric thickness. Finally, we compare the logic figures of merit of the NC-FinFET with those of the reference FinFET.

This work describes a novel simulation approach that combines machine learning (ML) and device modeling simulations. The device simulations are based on the quantum mechanical nonequilibrium Green’s function (NEGF) approach, and the ML method is an extension of a convolutional generative network. We have named our new simulation approach ML-NEGF. It is implemented in our in-house simulator called Nano-Electronics Simulation Software (NESS). The reported results demonstrate the improved convergence speed of the ML-NEGF method in comparison to the “standard” NEGF approach. The trained ML model effectively learns the underlying physics of nano-sheet transistor behavior, resulting in faster convergence of the coupled Poisson-NEGF self-consistency simulations. Quantitatively, our ML-NEGF approach achieves an average convergence speedup of 60%, substantially reducing the computational time while maintaining the same accuracy.

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.

The fully depleted silicon-on-insulator (FDSOI) technology has been a preferred choice for cryo-CMOS IC designers, but the combined effects of scaling both channel length and width, along with temperature variations, have not been extensively explored in the context of super low threshold voltage (SLVT) device technology. The key device figures of merit (FOMs), including threshold voltage (V_th), drain-induced barrier lowering (DIBL), subthreshold swing (SS), transconductance (g_m), and ON-resistance (R_ON), exhibit varying behaviors under changes in temperature and device scaling. Specifically, V_th, DIBL, and SS degrade in narrow-width devices at lower temperatures, while I_ON, g_m, and R_ON improve. For short-channel devices, the FOMs behave similar to their room-temperature counterparts, but with a temperature-dependent offset at cryogenic temperatures. The underlying temperature-dependent effects at cryogenic temperatures are further analyzed using TCAD simulations at 8 K and room temperature (RT).