In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O₂/He plasma by optimizing its bias voltage and O₂ flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current I_on, subthreshold slope (SS) and I_on/I_off ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (W_eff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si_0.7Ge_0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si_0.7Ge_0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si_0.7Ge_0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O₂ plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si_0.7Ge_0.3 channel. As a result, the selectivity of Si to Si_0.7Ge_0.3 can reach 32.84 with a signature of “rectangular” Si_0.7Ge_0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si_0.7Ge_0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, I_on/I_off ratio of 9 × 10⁵ and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under V_DS = V_GS = −0.8 V due to its large resistance of source and drain (9.2 × 10⁵ Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 10⁴ Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and I_on/I_off ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.

A high crystalline quality of SiGe fin with an Si-rich composition area using the replacement fin processing is systematically demonstrated in this paper. The fin replacement process based on a standard FinFET process is developed. A width of less than 20-nm SiGe fin without obvious defect impact both in the direction across the fin and in the direction along the fin is verified by using the high angle annular dark field scanning transmission electron microscopy and the scanning moiré fringe imaging technique. Moreover, the SiGe composition is inhomogenous in the width of the fin. This is induced by the formation of {111} facets. Due to the atomic density of the {111} facets being higher, the epitaxial growth in the direction perpendicular to these facets is slower than in the direction perpendicular to {001}. The Ge incorporation is then higher on the {111} facets than on the {001} facets. So, an Si-rich area is observed in the central area and on the bottom of SiGe fin.