Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH₂F₂/CH₄/O₂/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO₂. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

This article theoretically investigates the impact of charges at the ferroelectric/interlayer interface on the depolarization field of ferroelectric FET (FeFET) with metal/ferroelectric/interlayer/Si gate structure. The interfacial charges include fixed charges and trapped/detrapped charges. We find that the positive or negative interfacial charges (~10¹³ cm⁻²) can align the directions of the depolarization field and corresponding polarization in the ferroelectric. This article may provide insight into the device design of FeFET.

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high- ${k}$ metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed.

In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O₂/He plasma by optimizing its bias voltage and O₂ flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current I_on, subthreshold slope (SS) and I_on/I_off ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (W_eff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.

Complementary field-effect transistor is considered to be one of the most promising structures to replace gate-all-around (GAA) field-effect transistors after 2 nm node and extend Moore’s Law. In this work, we develop the nanosheet (NS) count design strategy to address the mobility mismatch of electron and hole in standard complementary FET (CFET) cells, that is, nine-stage ring oscillator (RO), 6T-SRAM cell. The device characteristics are obtained by state-of-the-art physics-based TCAD simulations, and high-accuracy 3-D parasitic extraction is implemented in the device to circuit co-optimization flow. The simulation result of RO and SRAM circuits reveals that altering the ratio of nFET NSs (nNSs) and pFET NSs (pNSs) can match the mobility of electrons and holes, thus optimizing the performance and power of different circuits for different applications. For CFETs in nine-state RO cells, the CFET with four pNS channels and two nNS channels shows a 10% increase in frequency and 6% decrease in capacitance, but only a 3% increase in power consumption when compared to the CFET with three pNS channels and three nNS channels. Also take the “3 $+$ 3” CFET as benchmark, for CFETs in SRAM cells, the “4 $+$ 2” CFET delivers 10% extra static noise margin (SNM) and 8% $\textit{I}_{\text{leak}}$ decrease, but the “1 $+$ 2” CFET offers 12% extra SNM with 20% $\textit{I}_{\text{leak}}$ increase, and advantage in terms of manufacturing process complexity.

This article presents a physics-based simulation study of a Si-core-SiGe-shell gate-all-around (GAA) nanosheet FET (NSFET). The numerical simulations employ various models including 1) an elastic model for lattice mismatch-induced stress in the core/shell structure; 2) the ${k}\cdot {p}$ method with a Poisson solver for the electrostatics; 3) Kubo-Greenwood model for low-field mobility calculation with surface roughness fit with experimental results; and 4) multi-subband Boltzmann transport equation (SBTE) for the high-field transfer characteristics. The study evaluates the effect of channel/wafer orientation, Ge component ratio ${x}$ in SiGe-shell region, core thickness ${T} _{\text {core}}$ , and surface roughness on electrostatics and transport properties. The Si/SiGe core/shell structure can be an additional performance knob for advanced technology node beyond 3 nm due to the following key physics: 1) thin SiGe-shell region with a high Ge component ratio tends to exhibit higher compressive stress in the shell region due to lattice mismatch; 2) holes are mainly confined in the SiGe-shell region under compressive strain at ON-state, leading to a significant enhancement in ${I} _{ \mathrm{ON}}$ for pMOS devices; and 3) core/shell devices exhibit lower hole density at OFF-state in the channel compared with Si-channel device, resulting in current leakage reduction. Finally, the proposed Si-core-SiGe-shell pMOS device achieves a 30.5% enhancement of ${I} _{ \mathrm{ON}}$ at ${T} _{\text {core}}= {3}$ nm and ${x}$ = 0.1, and two orders of magnitude higher ON- OFF ratio at ${T} _{\text {core}}$ = 2 nm and ${x}$ = 0.1, compared to the single Si-channel pMOS device. The results suggest that the proposed core-shell structure is a potential candidate for 3-nm node pMOS and beyond.