Artificial Intelligence (AI) and, in particular, Machine Learning (ML), have emerged to be utilized in various applications due to their capability to learn how to solve complex problems. Over the past decade, rapid advances in ML have presented Deep Neural Networks (DNNs) consisting of a large number of neurons and layers. DNN Hardware Accelerators (DHAs) are leveraged to deploy DNNs in the target applications. Safety-critical applications, where hardware faults/errors would result in catastrophic consequences, also benefit from DHAs. Therefore, the reliability of DNNs is an essential subject of research. In recent years, several studies have been published accordingly to assess the reliability of DNNs. In this regard, various reliability assessment methods have been proposed on a variety of platforms and applications. Hence, there is a need to summarize the state-of-the-art to identify the gaps in the study of the reliability of DNNs. In this work, we conduct a Systematic Literature Review (SLR) on the reliability assessment methods of DNNs to collect relevant research works as much as possible, present a categorization of them, and address the open challenges. Through this SLR, three kinds of methods for reliability assessment of DNNs are identified, including Fault Injection (FI), Analytical, and Hybrid methods. Since the majority of works assess the DNN reliability by FI, we characterize different approaches and platforms of the FI method comprehensively. Moreover, Analytical and Hybrid methods are propounded. Thus, different reliability assessment methods for DNNs have been elaborated on their conducted DNN platforms and reliability evaluation metrics. Finally, we highlight the advantages and disadvantages of the identified methods and address the open challenges in the research area. We have concluded that Analytical and Hybrid methods are light-weight yet sufficiently accurate and have the potential to be extended in future research and to be utilized in establishing novel DNN reliability assessment frameworks.

Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose design-for-testability (DFT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults open and shorts between adjacent interconnection lines are covered by the method. The approach allows reaching higher fault coverage in comparison to the recent DFT based solutions

The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to extend the use of test configurations for diagnosis purposes and to propose a method for locating faults in the NoC interconnection infrastructure. Additionally, a new concept of functional switch faults, called link faults, is introduced. The approach is well scalable (complexity is square root of the number of switches) and it is capable of unambiguously pinpointing the faulty links inside the switching network.

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

Sensor networks provide services to a broad range of applications ranging from intelligence service surveillance to weather forecasting. While most of the sensor networks are terrestrial, Underwater Sensor Networks (USN) are an emerging area. One of the unavoidable and increasing challenges for modern USN technology is tolerating faults, i.e., accepting that hardware is imperfect, and coping with it. Fault Tolerance tends to have more impact in underwater than in terrestrial environment as the latter is generally more forgiving. Moreover, reaching the malfunctioning devices for replacement and maintenance under water is harder and more costly. The current paper is the first to provide an overview of fault-tolerant, particularly cross-layer fault-tolerant, techniques in USNs. In the paper, we present a systematic survey of the techniques, introduce a taxonomy of the Fault Tolerance tasks, present a categorized list of articles, and list the open research issues within the area.

The study proposes a new concept of test and diagnosis in regular mesh-like network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As it will be shown, such configurations can be applied for achieving near-100% structural fault coverage for the network switches. Additionally, a concept of functional switch faults, called link faults, is introduced. The approach is scalable (complexity grows linearly with respect to the number of switches) and it is capable of unambigously pinpointing the faulty links inside the switching network. Current paper also presents a set of design-for-testability (DfT) techniques for the application of test patterns from the external boundary of a NoC. The authors have implemented a parametrisable switching network and developed a set of DfT structures to support testing of network switches using external test configurations. The proposed structures include resource loopback for testing the crossbar multiplexer of the resource connection, a modification to the control part to force YX routing and a compact logic built-in self test (BIST) for the control unit. Experiments show that the proposed structures allow near-100% test coverage at the expense of less than 4% of extra switch area.