Artificial Intelligence (AI) and, in particular, Machine Learning (ML), have emerged to be utilized in various applications due to their capability to learn how to solve complex problems. Over the past decade, rapid advances in ML have presented Deep Neural Networks (DNNs) consisting of a large number of neurons and layers. DNN Hardware Accelerators (DHAs) are leveraged to deploy DNNs in the target applications. Safety-critical applications, where hardware faults/errors would result in catastrophic consequences, also benefit from DHAs. Therefore, the reliability of DNNs is an essential subject of research. In recent years, several studies have been published accordingly to assess the reliability of DNNs. In this regard, various reliability assessment methods have been proposed on a variety of platforms and applications. Hence, there is a need to summarize the state-of-the-art to identify the gaps in the study of the reliability of DNNs. In this work, we conduct a Systematic Literature Review (SLR) on the reliability assessment methods of DNNs to collect relevant research works as much as possible, present a categorization of them, and address the open challenges. Through this SLR, three kinds of methods for reliability assessment of DNNs are identified, including Fault Injection (FI), Analytical, and Hybrid methods. Since the majority of works assess the DNN reliability by FI, we characterize different approaches and platforms of the FI method comprehensively. Moreover, Analytical and Hybrid methods are propounded. Thus, different reliability assessment methods for DNNs have been elaborated on their conducted DNN platforms and reliability evaluation metrics. Finally, we highlight the advantages and disadvantages of the identified methods and address the open challenges in the research area. We have concluded that Analytical and Hybrid methods are light-weight yet sufficiently accurate and have the potential to be extended in future research and to be utilized in establishing novel DNN reliability assessment frameworks.

This study describes the Computing Platforms (CPs) and the hardware reliability issues of Unmanned Aerial Vehicles (UAVs), or drones, which recently attracted significant attention in mission and safety-critical applications demanding a failure-free operation. While the rapid development of the UAV technologies was recently reviewed by survey reports focusing on the architecture, cost, energy efficiency, communication, and civil application aspects, the computing platforms’ reliability perspective was overlooked. Moreover, due to the rising complexity and diversity of today’s UAV CPs, their reliability is becoming a prominent issue demanding up-to-date solutions tailored to the UAV specifics. The objective of this work is to address this gap, focusing on the hardware reliability aspect. This research studies the UAV CPs deployed for representative applications, specific fault and failure modes, and existing approaches for reliability assessment and enhancement in CPs for failure-free UAV operation. This study indicates how faults and failures occur in the various system layers of UAVs and analyzes open challenges. We advocate a concept of a cross-layer reliability model tailored to UAVs’ onboard intelligence and identify directions for future research in this area.

Today, unmanned aerial vehicles (UAVs) or drones are increasingly used to enable and support multi-access edge computing (MEC). However, transferring data between nodes in such dynamic networks implies considerable latency and energy consumption, which are significant issues for practical real-time applications. In this paper, we consider an autonomous swarm of heterogeneous drones. This is a general architecture that can be used for applications that need in-field computation, e.g. real-time object detection in video streams. Collaborative computing in a swarm of drones has the potential to improve resource utilization in a real-time application i.e., each drone can execute computations locally or offload them to other drones. In such an approach, drones need to compete for using each other’s resources; therefore, efficient orchestration of the communication and offloading at the swarm level is essential. The main problem investigated in this work is computation offloading between drones in a swarm. To tackle this problem, we propose a novel federated learning (FL)-based fast and fair offloading strategy with a rating method. Our simulation results demonstrate the effectiveness of the proposed strategy over other existing methods and architectures with average improvements of −23% in energy consumption, −15% in latency, +18% in throughput, and +9% in fairness.

Deep Neural Network (DNN) hardware accelerators are essential in a spectrum of safety-critical edge-AI applications with stringent reliability, energy efficiency, and latency requirements. Multiplication is the most resource-hungry operation in the neural network’s processing elements. This paper proposes a scalable adaptive fault-tolerant approximate multiplier (AdAM) tailored for ASIC-based DNN accelerators at the algorithm and circuit levels. AdAM employs an adaptive adder that relies on an unconventional use of input Leading One Detector (LOD) values for fault detection by optimizing unutilized adder resources. A gate-level optimized LOD design and a hybrid adder design are also proposed as a part of the adaptive multiplier to improve the hardware performance. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the Triple Modular Redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR while at the same time utilizing 2.74× less area and with 39.06% less power-delay product compared to the exact multiplier. Moreover, it has similar area, delay, and power consumption parameters compared to the state-of-the-art approximate multipliers with similar accuracy while providing fault detection and mitigation capability.

Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants.