Deep learning-based object detection in remote sensing images is an important yet challenging task due to a series of difficulties, such as complex geometry scene, dense target quantity, and large variant in object distributions and scales. Moreover, algorithm designers also have to make a trade-off between model’s complexity and accuracy to meet the real-world deployment requirements. To deal with these challenges, we proposed a lightweight YOLO-like object detector with the ability to detect objects in remote sensing images with high speed and high accuracy. The detector is constructed with efficient channel attention layers to improve the channel information sensitivity. Differential evolution was also developed to automatically find the optimal anchor configurations to address issue of large variant in object scales. Comprehensive experiment results show that the proposed network outperforms state-of-the-art lightweight models by 5.13% and 3.58% in accuracy on the RSOD and DIOR dataset, respectively. The deployed model on an NVIDIA Jetson Xavier NX embedded board can achieve a detection speed of 58 FPS with less than 10W power consumption, which makes the proposed detector very suitable for low-cost low-power remote sensing application scenarios.

NνDEx is an experiment proposed to search for the neutrinoless double-beta decay of ⁸² Se using a high-pressure gaseous time projection chamber. In Phase-I of the experiment, the NνDEx-100 detector is filled with about 100 kg SeF ₆ . The readout and DAQ systems are crucial components of the experiment. The two-dimensional pixelated readout plane, consisting of approximately 15,000 sensors for charge measurement, is placed at one end-cap of the chamber. The electrode and charge-sensitive preamplifier in each sensor collect drifted ions and amplify the signal, with the analog output transmitted to a digital ASIC, where an internal ADC continuously digitizes the pulse. All digital ASICs on the plane form two routing networks, utilizing four pairs of bidirectional I/Os in each chip. The digitized waveform data from all chips is transmitted towards one edge of the plane via these two networks. Data aggregation modules at the edge aggregate slow parallel data links to fast serial data links, which are then connected to the DAQ system in the back-end. This paper aims to introduce the design and testing of the demonstrator system for the full digital readout chain, including a digital chips array, a data aggregation module and the back-end DAQ system.

NνDEx is an upcoming neutrino-less double-beta decay experiment. A first small-scale prototype, named N νDEx-100, features a readout plane with a 0.9m diameter situated at one end-cap of its time projection chamber. This plane hosts around 10,000 charge measurement sensors requiring dedicated readout electronics. This manuscript introduces the prototype design of the readout electronics and its integration with the back-end data acquisition system, which is composed of dedicated firmware and software to handle the system control and data readout. In the front-end, the demonstration system is developed to house 19 sensors along with the necessary supporting circuitry. The functionality and performance of the entire demonstration system with Topmetal-S sensors are evaluated, and the ion measurement capability of the system has been confirmed by tracking particles irradiated from the ²⁴¹ Am α source.

The Advanced Telecommunications Computing Architecture (ATCA) has been widely adopted in readout and trigger systems for nuclear and particle physics experiments. A scalable, modular ATCA platform has been developed to support high-performance signal processing for the Electron-Ion Collider in China and a fixed-target scattering experiment at the SHINE facility. The system integrates a versatile ATCA carrier board paired with a Rear Transition Module (RTM). It supports up to four mezzanine cards, enabling flexible configurations tailored to diverse processing tasks, including readout, data acquisition, and real-time trigger logic implementation. The carrier board is equipped with a high-performance XCKU15P Field Programmable Gate Array (FPGA), while the RTM incorporates an XCZU9EG Soc (System on Chip) FPGA, primarily utilizing its integrated processing system for auxiliary functions. Additionally, the mezzanine cards can be fitted with FPGAs, significantly enhancing the processing capabilities and expanding interface options. High-speed interconnections between the carrier board, RTM, and mezzanine cards ensure efficient, high-throughput data transfer. For trigger applications, the system supports approximately 100 optical input fiber links, leveraging multiple FPGAs to execute complex online algorithms. This paper presents a comprehensive overview of the system design and performance evaluation. The hardware validation results confirm that the system serves as a robust platform for high-speed data transmission and digital signal processing.