The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of ℒ = 2 × 10³⁴ cm^-2 s^-1 was routinely achieved at the start of fills, twice the design luminosity. For Run 3, accelerator improvements, notably luminosity levelling, allow sustained running at an instantaneous luminosity of ℒ = 2 × 10³⁴ cm^-2 s^-1, with an average of up to 60 interactions per bunch crossing. The ATLAS detector has been upgraded to recover Run 1 single-lepton trigger thresholds while operating comfortably under Run 3 sustained pileup conditions. A fourth pixel layer 3.3 cm from the beam axis was added before Run 2 to improve vertex reconstruction and b-tagging performance. New Liquid Argon Calorimeter digital trigger electronics, with corresponding upgrades to the Trigger and Data Acquisition system, take advantage of a factor of 10 finer granularity to improve triggering on electrons, photons, taus, and hadronic signatures through increased pileup rejection. The inner muon endcap wheels were replaced by New Small Wheels with Micromegas and small-strip Thin Gap Chamber detectors, providing both precision tracking and Level-1 Muon trigger functionality. Trigger coverage of the inner barrel muon layer near one endcap region was augmented with modules integrating new thin-gap resistive plate chambers and smaller-diameter drift-tube chambers. Tile Calorimeter scintillation counters were added to improve electron energy resolution and background rejection. Upgrades to Minimum Bias Trigger Scintillators and Forward Detectors improve luminosity monitoring and enable total proton-proton cross section, diffractive physics, and heavy ion measurements. These upgrades are all compatible with operation in the much harsher environment anticipated after the High-Luminosity upgrade of the LHC and are the first steps towards preparing ATLAS for the High-Luminosity upgrade of the LHC. This paper describes the Run 3 configuration of the ATLAS detector.

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

In high energy physics and nuclear physics experiments, particularly the ones based on a particle accelerator, the data rate from the detector is usually in the order of terabytes per second. These high throughput data from detector front-end electronics (FEEs) need to be transmitted to the back-end computing farm for high-level event selection and building. A data acquisition (DAQ) system with the features of high density, scalable, and easily upgradeable is crucial to simplify the readout architecture of the whole experiment. This article will introduce the design of a generic high bandwidth PCIe card, which can be used as the important input–output card in a scalable DAQ system. It can factorize FEEs from data handling and reduce the amount of custom hardware in favor of scalable detector-independent commercial hardware and software. Besides the 48 channels of bidirectional high-speed fiber optical links with front ends, it also supports to synchronize with the experiment timing system and to fan-out the clock and trigger information with a fixed latency to the FEEs.

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) calorimeters will be installed during the second long shutdown of the Large Hadron Collider (LHC) in 2019-2020 which will enable enhanced instantaneous luminosities during LHC Run 3 from 2021 through 2023. In this trigger upgrade, so-called supercells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the Level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will process and digitize up to 320 channels of supercell signals, and transmit them via 40 fiber optical links to the back-end where the data are further processed and transmitted to the trigger processors. Five pairs of bidirectional GBT links are used for slow control and monitoring between LTDB and the Front-End LInk eXchange (FELIX) in the ATLAS Trigger and Data Acquisition (TDAQ) system. The LTDB also outputs 64 summed analog legacy signals to the current Tower Builder Board via a new baseplane. A test system for the production of 124 LTDBs has been developed, supporting configuration and calibration of all ASICs on the LTDB, as well as evaluation of full LTDB functionality.