NarrowBand Internet of Things (NB-IoT) is an emerging cellular IoT technology that offers attractive features for deploying low-power wide-area networks suitable for implementing massive machine-type communications. NB-IoT features include, e.g., extended coverage and deep penetration for massive connectivity, longer battery-life, appropriate throughput, and desired latency at lower bandwidth. Regarding the device energy consumption, NB-IoT is mostly underestimated for its control and signaling overheads, which calls for a better understanding of the energy consumption profiling of an NB-IoT radio transceiver. With this aim, this work presents a thorough investigation of the energy consumption profiling of the radio resource control (RRC) communication protocol between an NB-IoT radio transceiver and a cellular base station. Using two different commercial off the shelf NB-IoT boards and two mobile network operators (MNOs) NB-IoT test networks operational at Tallinn University of Technology, Estonia, we propose an empirical baseline energy consumption model. Based on comprehensive analyses of the profile traces from the widely used BG96 NB-IoT module operating in various states of the RRC protocol, our results indicate that the proposed model accurately depicts the baseline energy consumption of an NB-IoT radio transceiver while operating at different coverage class levels. The evaluation errors of our proposed model vary between 0.33% and 15.38%.

This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over $GF\left(2^{233}\right)$. Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of $\frac{throughput}{area}$ is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

Machine Learning (ML) techniques can play a pivotal role in energy efficient IoT networks by reducing the unnecessary data from transmission. With such an aim, this work combines a low-power, yet computationally capable processing unit, with an NB-IoT radio into a smart gateway that can run ML algorithms to smart transmit visual data over the NB-IoT network. The proposed smart gateway utilizes supervised and unsupervised ML algorithms to optimize the visual data in terms of their size and quality before being transmitted over the air. This relaxes the channel occupancy from an individual NB-IoT radio, reduces its energy consumption and also minimizes the transmission time of data. Our on-field results indicate up to 93% reductions in the number of NB-IoT radio transmissions, up to 90.5% reductions in the NB-IoT radio energy consumption and up to 90% reductions in the data transmission time.

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over $GF\left(2^{163}\right)$ with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over $GF\left(2^{163}\right)$ is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 $\mathsf{\mu }$s for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 $\mathsf{\mu }$W) and Kintex-7 (61 $\mathsf{\mu }$W) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over $GF\left(2^{163}\right)$. To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 $\mathsf{\mu }$W, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 $\mathsf{\mu }$s. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 $\mathsf{\mu }$s latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 $\mathsf{\mu }$W power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., $163, 233, 283, 409$ and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most relevant state-of-the-art multipliers. All multiplier architectures are implemented in Verilog HDL using the Vivado IDE tool. The implementation results are reported on a 28 nm Virtex-7 FPGA technology. The dedicated multipliers utilize slices of 1182 (for $m=163$), 1451 (for $m=233$), 1589 (for $m=283$), 2093 (for $m=409$) and 3451 (for $m=571$). Moreover, our dedicated designs can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Similarly, for all supported binary fields, our scalable architecture (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 μs for one finite field multiplication and (iv) consumes 3.905 W power. The proposed scalable digit-parallel architecture is more area-efficient than most recent state-of-the-art multipliers. Consequently, the reported results and comparison to the state of the art reveal that the proposed architectures are well suited for cryptographic applications.