In order to compute the elliptic curve point addition and doubling, the unified point addition law provides better protection against side channel attacks. One of the elliptic curve models, providing the unified point addition, is Binary Huff Curves (BHC). Recently, a new unified method for BHC with improved security against side channel attacks, has been proposed. Therefore, an optimized hardware architecture in terms of higher clock frequency and throughput for the new unified point addition method is required. Consequently, this article has three major contributions: The first contribution is to modify the unified addition law from hardware implementation point of view, resulting 31% decrease in memory requirements. The second contribution is the analysis of memory optimized unified law in the context of pipelining. In this regard, this article proposes an instruction scheduling policy for a 2-stage pipelined architecture which provides 36% reduction in the number of required clock cycles, 14.3% improvement in clock frequency, 53.2% decrease in computation time and 54.5% improvement in throughput/area. Finally, the third contribution is to propose a 4-stage pipelined architecture. The proposed 4-stage pipelined architecture provides an additional 19% improvement in clock frequency and 10% increase in throughput, as compared to the 2-stage pipelined architecture.

The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over $GF\left(2^{233}\right)$. There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-$bit$ finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over $GF\left(2^{233}\right)$ on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over $GF\left(2^{163}\right)$ with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over $GF\left(2^{163}\right)$ is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 $\mathsf{\mu }$s for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 $\mathsf{\mu }$W) and Kintex-7 (61 $\mathsf{\mu }$W) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over $GF\left(2^m\right)$. This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for $GF\left(2^{233}\right)$ on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources.

This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over $GF\left(2^{163}\right)$ and $GF\left(2^{571}\right)$. The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over $GF\left(2^{163}\right)$ and $GF\left(2^{571}\right)$ on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.

Time synchronization is vital for accurate data collection and processing in sensor networks. Sensors in these networks often operate under fluctuating conditions. However, an accurate timekeeping mechanism is critical even in varying network conditions. Consequently, a synchronization method is required in sensor networks to ensure reliable timekeeping for correlating data accurately across the network. In this research, we present a novel dynamic NTP (Network Time Protocol) algorithm that significantly enhances the precision and reliability of the generalized NTP protocol. It incorporates a dynamic mechanism to determine the Round-Trip Time (RTT), which allows accurate timekeeping even in varying network conditions. The proposed approach has been implemented on an FPGA and a comprehensive performance analysis has been made, comparing three distinct NTP methods: dynamic NTP (DNTP), static NTP (SNTP), and GPS-based NTP (GNTP). As a result, key performance metrics such as variance, standard deviation, mean, and median accuracy have been evaluated. Our findings demonstrate that DNTP is markedly superior in dynamic network scenarios, a common characteristic in sensor networks. This adaptability is important for sensors installed in time-critical networks, such as real-time industrial IoTs, where precise and reliable time synchronization is necessary.