The robustness of Bayesian neural networks (BNNs) to real-world uncertainties and incompleteness has led to their application in some safety-critical fields. However, evaluating uncertainty during BNN inference requires repeated sampling and feed-forward computing, making them challenging to deploy in low-power or embedded devices. This article proposes the use of stochastic computing (SC) to optimize the hardware performance of BNN inference in terms of energy consumption and hardware utilization. The proposed approach adopts bitstream to represent Gaussian random number and applies it in the inference phase. This allows for the omission of complex transformation computations in the central limit theorem-based Gaussian random number generating (CLT-based GRNG) method and the simplification of multipliers as and operations. Furthermore, an asynchronous parallel pipeline calculation technique is proposed in computing block to enhance operation speed. Compared with conventional binary radix-based BNN, SC-based BNN (StocBNN) realized by FPGA with 128-bit bitstream consumes much less energy consumption and hardware resources with less than 0.1% accuracy decrease when dealing with MNIST/Fashion-MNIST datasets.

Currently, untrusted third-party entities are increasingly involved in various stages of IC design and manufacturing, posing a significant threat to the reliability and security of SoCs due to the presence of hardware Trojans (HTs). In this paper, gate-level HT detection methods based on graph neural networks( GNNs) are established to overcome the defects of existing machine learning, which makes it difficult to characterize circuit connection relationships. We introduce harmonic centrality in the feature engineering of gate-level HT detection, which reflects the positional information of nodes and their adjacent nodes in the graph, thereby enhancing the quality of feature engineering. We use the golden section weight optimization algorithm to configure penalty weights to alleviate the problem of extreme data imbalance. In the SAED database, GraphSAGE-LSTM model obtained a TPR of 88.06% and an average F1 score of 90.95%. In the combined HT netlist of LEDA datasets, GraphSAGE-POOL model obtains a TPR of 88.50% and the best F1 score of 92.17%. In sequential HT netlist, GraphSAGE-LSTM model performs optimally, with a TPR of 98.25% and an average F1 score of 98.59%. Compared to existing detection models, the F1 score is enhanced by 8.86% and 2.48% on combined and sequential HT datasets, respectively.

Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been demonstrated as one of the most promising candidates due to its endurance and compatibility. However, the integration density of SRAM-based PIM is much lower than other nonvolatile memory-based ones, due to its inherent 6T structure for storing a single bit. Within comparable area constraints, SRAM-based PIM exhibits notably lower capacity. Thus, aiming to unleash its capacity potential, we propose DDC-PIM, an efficient algorithm/architecture co-design methodology that effectively doubles the equivalent data capacity. At the algorithmic level, we propose a filter-wise complementary correlation (FCC) algorithm to obtain a bitwise complementary pair. At the architecture level, we exploit the intrinsic cross-coupled structure of 6T SRAM to store the bitwise complementary pair in their complementary states $(Q/\overline {Q})$ , thereby maximizing the data capacity of each SRAM cell. The dual-broadcast input structure and reconfigurable unit support both depthwise and pointwise convolution, adhering to the requirements of various neural networks. Evaluation results show that DDC-PIM yields about $2.84\times $ speedup on MobileNetV2 and $2.69\times $ on EfficientNet-B0 with negligible accuracy loss compared with PIM baseline implementation. Compared with state-of-the-art SRAM-based PIM macros, DDC-PIM achieves up to $8.41\times $ and $2.75\times $ improvement in weight density and area efficiency, respectively.

The radar cross section (RCS) reduction of hypersonic targets by radar absorbing materials (RAM) coating under different reentry cases is analyzed in the C and X bands frequency range normally used for radar detection. The physical optics method is extended to both the inhomogeneous plasma sheath and RAM layer present simultaneously. The simulation results show that the absorbing coating can reduce the RCS of the plasma cloaking system and its effectiveness is related to the maximum plasma frequency. Moreover, the amount of the RCS decrease, its maxima, and the corresponding optimal RAM thickness depend on the non-uniformity and parameters of the plasma sheath. In addition, the backward RCS of the flight vehicle shrouded by plasma shielding and man-made absorber is calculated and compared to the bare cone.

Presents corrections to the paper, (Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”).

Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to the system. Ionizing radiation induced soft error is one of the major concerns in the design of electronic systems, especially in avionics or space applications. Nowadays, the majority of electronic systems relies on single-error correction, double-error detection (SEC-DED) codes to mitigate soft errors. However, the presence of multiple bit upsets is becoming more prevalent as CMOS technology scales down. In addition, state registers in FSMs usually have variable bit-widths and have strict requirement on encoding and decoding delay, which poses challenges for error mitigation techniques. This paper presents an Error Detection and Correction (EDAC) code for state register protection, which can achieve single-error correction, double-error correction and triple-adjacent-error correction (SEC-DEC-TAEC) ability. The proposed code can be used to protect data with 4n bit-width (n = 2,3,4,...) using one common encoder and decoder code block and introduces minimal delay. Experiment results show that the proposed code has better error correction ability than most existing MCU correction codes. Besides, it reduces area occupation by 30% and delay by 15% compared with Orthogonal Latin Square (OLS) code in the case of 8 bit-width data.