This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

In this work the influences of solid viscosity and the way to scale-down traditional drag models on the predicted hydrodynamics of Geldart A particles in a lab-scale gas-solid bubbling fluidized bed are investigated. To evaluate the effects of drag models, the modified Gibilaro et al. drag model (constant correction factor) and the EMMS drag model (non-constant correction factor) are tested. And the influences of solid viscosity are assessed by considering the empirical model proposed by Gidaspow et al. (1997, Turbulence, Viscosity and Numerical Simulation of FCC Particles in CFB. Fluidization and Fluid-particle Systems, AIChE Annual Meeting, Los Angeles, 58–62) and the models based on kinetic theory of granular flow (KTGF) with or without frictional stress. The resulting hydrodynamics by incorporating the different combinations of the drag model and solid viscosity model into two-fluid model (TFM) simulations are compared with the experimental data of Zhu et al. (2008, Detailed Measurements of Flow Structure inside a Dense Gas-Solids Fluidized Bed.” Powder Technological 180:339–349). The simulation results show that the predicted hydrodynamics closely depends on the setting of solid viscosity. When solid viscosity is calculated from the empirical model of Gidaspow et al., both drag models can reasonably predict the radial solid concentration profiles and particle velocity profiles. When the KTGF viscosity model without frictional stress is adopted, the EMMS drag model significantly over-estimates the bed expansion, whereas the modified Gibilaro et al. drag model can still give acceptable radial solid concentration profiles but over-estimate particle upwards and downwards velocity. When KTGF viscosity model with frictional stress is chosen, both drag models predict the occurrence of slugging. At this time, the particle velocity profiles predicted by EMMS drag model are still in well agreement with the experimental data, but the bed expansion is under-estimated.

A low phase noise quadrature LO-generator for dual-band wireless local area network (WLAN) applications is presented. The quadrature LO-generator is composed of a clock receiver, a CML divider, and two quadrature dividers for the dual-band, respectively. A clock receiver converts the single-ended clock to a differential signal. Then a quadrature divider with a 25% duty cycle generates four quadrature signals for mixers. The split-grounded architecture and multiply ground pads decrease the inductive component of ground impedance as well as the ground bounce of the single-ended input. The phase noise is -143dBc/Hz and -149dBc/Hz at 1MHz offset in the 2.4-GHz and 5-GHz bands, respectively.

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm² and consumes 23.86 mW.