Fixed-complexity sphere decoder (FSD) is one of the most promising techniques for the implementation of multiple-input multiple-output (MIMO) detection, with relevant advantages in terms of constant throughput and high flexibility of parallel architecture. The reported works on FSD are mainly based on software level simulations and a few details have been provided on hardware implementation. The authors present the study based on a four-nodes-per-cycle parallel FSD architecture with several examples of VLSI implementation in 4×4 systems with both 16-quadrature amplitude modulation (QAM) and 64-QAM modulation and both real and complex signal models. The implementation aspects and details of the architecture are analysed in order to provide a variety of performance-complexity trade-offs. The authors also provide a parallel implementation of log-likelihood-ratio (LLR) generator with optimised algorithm to enhance the proposed FSD architecture to be a soft-input soft-output (SISO) MIMO detector. To the authors best knowledge, this is the first complete VLSI implementation of an FSD based SISO MIMO detector. The implementation results show that the proposed SISO FSD architecture is highly efficient and flexible, making it very suitable for real applications.

Improving the quality of service (QoS) performance to support existing and upcoming real-time applications is critical for IEEE 802.11n/ac devices. The mechanisms of the media access control (MAC) layer, including the aggregate MAC protocol data unit (A-MPDU) aggregation, greatly affect the QoS performance in wireless local area networks (WLANs). To investigate the impact of the aggregation level on the QoS performance for real-time multimedia applications, a novel end-to-end delay model for the unsaturated settings is proposed in this paper. The presented model considers the gathering procedure of packets, queuing behaviors, and transmissions using the RTS/CTS (request to send/clear to send) mechanism on error-prone channels. Based on the model, a novel QoS-aware A-MPDU aggregation scheduler for IEEE802.11n/ac WLANs was shown to obtain better QoS performance with lower latency and less packet loss, a larger capacity to hold higher data rates, and more working nodes. The validation of the proposed model and the promotion of the proposed scheduler are well benchmarked by ns-3.

This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip's total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm ² and is implemented in a 130nm CMOS process.

In this letter, a new method is proposed to approximate n-input (n > 2) max* operation. Bi-variable Taylor series expansion, for the first time, is applied to approximate the correction term of n-input (n > 2) max* operation. It avoids the recursive computation of bi-variable Jacobian logarithm. To improve the approximation performance, multiple expansion points are considered. The proposed method is evaluated for 3GPP LTE turbo codes. The simulation results show that the approximation with five expansion points, applied with scaling factor to extrinsic information, has performance degradation of 0.01 dB compared with radix-4 Log-MAP algorithm. Furthermore, the approximation with three expansion points will bring minor performance loss but almost the same computational complexity compared with five expansion points.

This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

The QC-LDPC code, with its excellent error correction performance and hardware friendliness, has been identified as one of the channel encoding schemes by Wi-Fi 6. Shorting, puncturing, or repeating operations are needed to ensure that user data can be sent with integer symbols and complete rate matching. Due to the uncertainty of the user data size, the modulation’s selectivity, and the difference in the number of spatial streams, the receiver must deal with more than 10⁶ situations. At the same time, other computationally intensive tasks occupy the time slot budget of the receiver. Typical are demodulation and decoding. Hence, the receiver needs to quickly reverse the demodulated data process. This paper first proposes a co-processing method and VLSI architecture compatible with all code lengths, code rates, and processing parameters. The co-processor separates field and block splicing, simplifying the control logic. There is no throughput rate bottleneck, and the maximum delay is less than 1 us.