To address the limitations of typical coil detection systems and enhance the performance of traditional magnetic field imaging (MFI) systems, we propose a MFI system that uses a $4\times4$ array of anisotropic magnetoresistance (AMR) sensors. The core controller of the proposed system was designed using a pipelined parallelization algorithm and implemented on a high-speed field-programmable gate array (FPGA) in a fully hardware-based architecture. The designed MFI system can achieve parallel acquisition of magnetic field components from the 16-channel AMR sensor array, parallel data processing, parallel data transmission, and parallel computations in a single cycle of only 4 ms. Compared with typical detection systems, the proposed solution not only exhibits superior performance but can also provide dynamic visual representations of sensed information.

The increasing density of static random access memory (SRAM) in modern system-on-chip (SoC) architectures has intensified the need for efficient built-in self-test (BIST) solutions to ensure fault detection and repair. This article presents an optimized register transfer level (RTL)-BIST intellectual property core (IP core) that integrates a novel March mSR+ algorithm, providing a low-power, high-fault-coverage approach to embedded memory testing. Developed using high-level synthesis (HLS), the proposed framework enhances test efficiency while minimizing hardware complexity. Experimental results on field-programmable gate array (FPGA) implementations demonstrate that the March mSR+ algorithm achieves an 88.89% fault coverage while reducing power consumption compared with conventional March-based testing methods. These findings validate the effectiveness of the RTL-BIST framework in improving memory reliability for artificial intelligence (AI), high-performance computing (HPC), and safety-critical applications.