The rapid development of machine vision applications demands hardware that can sense and process visual information in a single monolithic unit to avoid redundant data transfer. Here, we design and demonstrate a monolithic vision enhancement chip with light-sensing, memory, digital-to-analog conversion, and processing functions by implementing a 619-pixel with 8582 transistors and physical dimensions of 10 mm by 10 mm based on a wafer-scale two-dimensional (2D) monolayer molybdenum disulfide (MoS ₂ ). The light-sensing function with analog MoS ₂ transistor circuits offers low noise and high photosensitivity. Furthermore, we adopt a MoS ₂ analog processing circuit to dynamically adjust the photocurrent of individual imaging sensor, which yields a high dynamic light-sensing range greater than 90 decibels. The vision chip allows the applications for contrast enhancement and noise reduction of image processing. This large-scale monolithic chip based on 2D semiconductors shows multiple functions with light sensing, memory, and processing for artificial machine vision applications, exhibiting the potentials of 2D semiconductors for future electronics.

This paper presents two kinds of low-cost antennas for D-band short-distance wireless communication applications. Both antennas are excited by a substrate integrated waveguide (SIW) feed line based on the printed circuit board (PCB) process. The first type is a stainless-steel-based horn antenna, fabricated by electric-discharging machining (EDM) process and selective laser melting (SLM) 3-D printing respectively for reducing cost. To integrate the horn antennas with the SIW feed line, a wideband transition structure from SIW to the rectangular waveguide is designed by suppressing higher-order eigenmodes. Experimental data show that the integrated horn antenna can achieve 18.9% (129.5 to 156.5 GHz) -10-dB impedance bandwidth and a peak gain of 15.46 dBi. The second type of antenna is a single-layer rectangular patch antenna fed by SIW. By locally widening the SIW feed line to generate an equivalent shunt capacitance instead of using complex resonators, a wide impedance bandwidth can be realized. The measured -10-dB impedance bandwidth and the peak gain of the patch antenna are 20.8% (125.3 to 154.4 GHz) and 7.26 dBi respectively. The two proposed antennas can provide comparable performance for different application requirements under the premise of a low fabrication cost.

This paper presents a high-gain D-band power amplifier (PA) fabricated with 28-nm CMOS technology for a sub-terahertz frequency modulated continuous wave imaging system. It adopts two-channel power combining using artificial transmission lines to absorb the parasitic capacitance of the ground-signal-ground pad. The layout of the transistors and neutralization capacitors are optimized to improve the maximum stable gain, stability, and robustness. Asymmetrically magnetically coupled resonators are used in inter-stage and input matching networks to extend the operating bandwidth. The PA achieves a peak power gain of 21.9 dB and maximum output power of 11.8 dBm with 10.7% of power-added efficiency. Also, this PA can achieve higher than 10 dBm output power over the frequency range of 120-150 GHz.

This article presents a high-power wideband power amplifier (PA) with a four-way power-combining technique for $D$ -band high-resolution radar. The power combiner is based on a two-section Chebyshev impedance converter to achieve a large bandwidth (BW) and is realized with slow wave coplanar waveguides (S-CPWs) to reduce the insertion loss and chip area. Therefore, our developed technique can provide broadband and low-loss power-combining scheme in a very compact size. A high-power PA with four-way combining has been fabricated in a 28-nm CMOS bulk technology. The unit PA uses low- $k$ transformer-based coupled-resonator networks to realize wideband matching. The measured results of the PA prototype demonstrate the peak gain of 22.6 dB, the saturated output power of 16.2 dBm, and the peak power added efficiency of 8.6% at 135 GHz with a 3-dB BW of 28 GHz from 124 to 152 GHz. Meanwhile, the total area of this PA die is merely 0.66 $\times$ 0.73 mm.

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) dummy capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm ² . With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5 MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for Nyquist input signal.

This paper presents a high-speed and low feed-through sampler with two-channel time-interleaved track-and-hold amplifiers (THAs). The THA is based on switched buffer with active inductors load such that wide bandwidth in track-mode and small-signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. With two-channel accurate on-chip clock and its distribution network, double sampling rate is achieved due to the two-channel time-interleaved structure used. The chip was fabricated in 65-nm RF-CMOS process with core area of 0.07 mm ² and power consumption of 211 mW. The measurements show that the S-parameters matched input and output up to 40 GHz with 19.3-GHz bandwidth in track-mode, the spurious-free-dynamic-range above 35 dB and total harmonic distortion below -30 dB up to 6 GHz when the sampling rate is 16.26 GS/s for one channel.