The voltage-gate-assisted spin-orbit-torque (VGSOT) writing scheme combines the advantages from voltage control of magnetic anisotropy (VCMA) and spin-orbit-torque (SOT) effects, enabling multiple benefits for magnetic random-access-memory (MRAM) applications. In this work, we give a complete description of the VGSOT writing properties on perpendicular magnetic tunnel junction (PMTJ) devices, and we propose a detailed methodology for their electrical characterization. The impact of gate assistance on the SOT switching characteristics is investigated using electrical pulses down to 400 ps. The VCMA coefficient $(\xi )$ extracted from the current-switching scheme is found to be the same as that from the magnetic-field-switch method, which is in the order of 15 fJ/Vm for 80–150-nm devices. Moreover, as expected from the pure electronic VCMA effect, $\xi$ is revealed to be independent of the writing speed and gate length. We observe that SOT switching current characteristics are modified linearly with gate voltage $(V_g)$, similar to that for the magnetic properties. We interpret this linear behavior as the direct modification of perpendicular magnetic anisotropy induced by VCMA. At $V_g=1\mathrm{V}$, the SOT write current is decreased by 25%, corresponding to a 45% reduction in total energy down to 30 fJ/bit at 400 ps speed for the 80-nm devices used in this study. To test the operation reliability, we investigate the gate-SOT pulse configurations and overlays, and we find that an extended gate duration is able to preserve maximized gate benefit and selectivity. Furthermore, the device-scaling criteria are proposed, and we reveal that the VGSOT scheme is of great interest, as it can mitigate the complex material requirements of achieving high SOT and VCMA parameters for scaled MTJs. Finally, we perform design-to-technology co-optimization analysis to show that VGSOT MRAM can enable high-density arrays close to two-terminal geometries, with high-speed performance and low-power operation, showing great potential for embedded memories as well as in memory computing applications at advanced technology nodes.

Current-induced spin-orbit torques (SOTs) enable fast and efficient manipulation of the magnetic state of magnetic tunnel junctions (MTJs), making them attractive for memory, in-memory computing, and logic applications. However, the requirement of the external magnetic field to achieve deterministic switching in perpendicularly magnetized SOT-MTJs limits its implementation for practical applications. Here, we introduce a field-free switching (FFS) solution for the SOT-MTJ device by shaping the SOT channel to create a "bend" in the SOT current. The resulting bend in the charge current creates a spatially nonuniform spin current, which translates into inhomogeneous SOT on an adjacent magnetic free layer enabling deterministic switching. We demonstrate FFS experimentally on scaled SOT-MTJs at nanosecond time scales. This proposed scheme is scalable, material-agnostic, and readily compatible with wafer-scale manufacturing, thus creating a pathway for developing purely current-driven SOT systems.

We simulate the spin torque-induced reversal of the magnetization in thin disks with perpendicular anisotropy at zero temperature. Disks typically smaller than 20 nm in diameter exhibit coherent reversal. A domain wall is involved in larger disks. We derive the critical diameter of this transition. Using a proper definition of the critical voltage, a macrospin model can account perfectly for the reversal dynamics when the reversal is coherent. The same critical voltage appears to match with the micromagnetics switching voltage regardless of the switching path.

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

To get stable perpendicularly magnetized tunnel junctions at small device dimensions, composite free layers that comprise two MgO/FeCoB interfaces as sources of interface anisotropy are generally used. Proper cristallisation and annealing robustness is typically ensured by the insertion of a spacer layer of the early transition metal series within the FeCoB layer. We study the influence of the spacer thickness and growth condition on the switching metrics of tunnel junctions thermally annealed at 400°C for the case of 1-4 Å Ta spacers. Thick Ta spacer results in a large anisotropies indicative of a better defined top FeCoB/MgO interface, but this is achieved at the systematic expense of a stronger damping. For the best anisotropy-damping compromise, junctions of diameter 22 nm can still be stable and spin-torque switched. Coercivity and inhomogeneous linewidth broadening, likely arising from roughness at the FeCoB/Ta interface, can be reduced if a sacrificial Mg layer is inserted before the Ta spacer deposition.