The Kondo effect has been observed in a single gate-tunable atom. The measurement device consists of a single As dopant incorporated in a silicon nanostructure. The atomic orbitals of the dopant are tunable by the gate electric field. When they are tuned such that the ground state of the atomic system becomes a (nearly) degenerate superposition of two of the silicon valleys, an exotic and hitherto unobserved valley Kondo effect appears. Together with the “regular” spin Kondo, the tunable valley Kondo effect allows for reversible electrical control over the symmetry of the Kondo ground state from an SU(2) to an SU(4) configuration.

In this letter, we investigate contacts of a low work function rare-earth metal, La, and its silicides on n-Si. LaSi _x /n ^- -Si contacts show low Schottky barrier height (φ _b ) of around 0.25-0.4 eV and promisingly low contact resistivity (ρ _c ) on moderately doped n ⁺ -Si. However, on highly doped n ⁺⁺ -Si, we find Pc of LaSi _x near one order higher than the TiSi _x control. This experiment indicates that low φ _b does not guarantee low Pc on highly doped substrates. We further discuss reasons behind this phenomenon.

We report the first demonstration of a super-steep subthreshold slope (SS) (the smallest ever reported experimentally) with ultra-thin BOX (UTBOX) FDSOI standard CMOS transistors. Record steep SS of 72μV/dec for L _g =25nm and 58μV/dec for L _g =55nm at room temperature are achieved with low voltages. The device also exhibits high ON-state current (~100μA/μm), as compared to other devices from this class. As a result, I _ON /I _OFF ratio of 10 ⁸ is realized with 0.5V gate swing for L _g =55nm MOSFETs. The excellent reliability is also demonstrated.

International audienceIn this paper, DC and noise measurements on strained and unstrained SOI p-FinFETs were performed at cryogenic temperatures (10 K) in order to evaluate the device performances and study the low frequency noise mechanisms. The main electrical parameters (threshold voltage, subthreshold swing, mobility, etc.) are investigated and compared to those found at 80 K and 300 K. The low frequency noise analysis clearly shows that from 300 K to 10 K, the carriers number fluctuation dominates the flicker noise in the channel in weak inversion, while the access resistances noise contribution prevails in strong inversion. 1/fc noise has been observed with c varying with the temperature, which implies a non-uniformity of the active trap density in the oxide depth. The noise of the access resistances at 300 K originates from mobility fluctuations, while at low temperature operation it seems to have a trapping-detrapping origin

${\mathrm{Si}}_{1-x}{\mathrm{Ge}}_x/\mathrm{Si}$Si1−xGex/Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of ${\mathrm{Si}}_{1-x}{\mathrm{Ge}}_x$Si1−xGex has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity (microloading on a micrometer scale and gas depletion on a wafer scale) and facet formation must be solved. In this paper, we give a detailed overview of our selective ${\mathrm{Si}}_{1-x}{\mathrm{Ge}}_x$Si1−xGex growth process in a standard production-oriented chemical vapor deposition system for Ge contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content (no microloading) and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques $(\sim 2\%).$(∼2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer quality is further demonstrated by the performance of ${\mathrm{Si}}_{1-x}{\mathrm{Ge}}_x$Si1−xGex heterojunction bipolar transistors (0.35 and 0.25 μm technology), and p-type ${\mathrm{Si}}_{1-x}{\mathrm{Ge}}_x$Si1−xGex heterojunction metal oxide semiconductor devices (effective gate length down to 70 nm). © 2003 The Electrochemical Society. All rights reserved.