Learning with error (LWE) over the ring based on binary distribution (ring-BinLWE) has become a potential Internet-of-Things (IoT) confidentiality solution with its anti-quantum attack properties and uncomplicated calculations. Compared with ring-LWE based on discrete Gaussian distribution, the decryption scheme of ring-LWE based on binary distribution needs to be re- determined due to the asymmetry of the error distribution. The direct application of the ring-LWE decryption function based on discrete Gaussian distribution can cause serious misjudgment. In this article, we propose a more accurate and robust decryption scheme for ring-BinLWE based on 2’s complement ring. Compared with the previous decryption function, the re- derived decryption function significantly improves the decoding rate by 50%. Furthermore, based on the proposed decryption function, high-performance, and lightweight hardware architectures for terminal devices in IoT are, respectively, proposed, which are scalable and can be easily adapted to ring-BinLWE hardware deployment with other parameter sets. When the parameter set is $n\,\,=$ 256, $q\,\,=$ 256, the high-performance implementation consumes 7.6k LUTs, 6.2k FFs, and 2.3k SLICEs on Spartan 6 field-programmable gate array (FPGA) platform. Compared with the previous implementation, our resource overhead increases by only 23% while the decryption accuracy is significantly improved by 50%. The lightweight implementation for parameter set $n\,\,=$ 256, $q\,\,=$ 256 consumes only 230 LUTs, 338 FFs, and 84 SLICEs on the Spartan 6 FPGA platform. Compared with the previous work, the area $\times $ time (AT) is reduced by 47.8%, which is more suitable for deployment on resource-constrained IoT nodes.

As the Internet of Things (IoT) expands explosively existing network connections, the transmission and processing of private data is facing more serious threats of leakage and theft. Classical public key encryption schemes are difficult to guarantee strong security protection, because the mathematically hard problems they rely on are no longer difficult to solve under the rapid development of quantum computing. Therefore, a more high-performance and quantum-resistant encryption scheme Ring-ExpLWE is proposed, in which the error vector is sampled in the exponential distribution instead of the binary distribution in the previous Ring-BinLWE. We evaluate the Ring-ExpLWE’s security level by analyzing the runtime under quantum hybrid attack and comparing the standard deviation of the noise polynomial coefficients. Compared with Ring-BinLWE, the proposed Ring-ExpLWE requires larger runtime for quantum hybrid attack and has a more discrete noise distribution. Therefore, Ring-ExpLWE can provide a higher security level under the same parameter set. Moreover, the high-performance software and hardware implementations for the Ring-ExpLWE scheme are proposed, respectively. Based on the Cortex-M3 microprocessor platform, encryption, and decryption only require 35.6 and 17.8 ms in our software implementation, respectively. Compared with the previous Ring-BinLWE schemes, while significantly improving the security level, the Area $\times $ Time (AT) of our high-performance and lightweight hardware implementations is reduced by 49.2% and 49.5%, respectively, when the FPGA platform is Spartan 6.

The arbitrarily connected nature of IoT has led to an explosion in the number of embedded devices accessed. These devices typically store and process large amounts of private and critical data. Most of these data are transmitted in plaintext over the bus, which is vulnerable to attacks such as theft, leakage, tampering, and even control flow hijacking. Encryption and authentication of memory data can effectively alleviate these problems. Existing solutions introduce significant performance overhead while providing data protection. Therefore, in this article, we propose a low-latency, high-performance transparent memory data encryption and authentication hardware protection scheme based on Ascon-128, in which the multistage pipeline design and the optimization of address labels effectively reduce the encryption/decryption latency and the size and storage overhead of nonce data. Based on the designed hardware architecture, the performance overhead introduced is evaluated in terms of bandwidth, latency, runtime, and score using multiple test programs on a CVA6-32-bit RISC-V SoC platform. The measured results from TinyMemBench demonstrate that the memory read and write bandwidth introduced by the proposed transparent memory data encryption and authentication scheme is reduced by 10.2% and 5.6%, respectively. For real intensive computational loads, the average runtime of Crystal-Dilithium and Crystal-Kyber increases by 6.32% and 6.42%, respectively, under three different parameter sets.

At present, the embedded systems are facing various kinds of attacks, especially for the data stored in the external memories. This paper presents a hardware-enhanced protection method to protect the data integrity and confidentiality at runtime, preventing the data from spoofing attack, splicing attack, replay attack, and some malicious analysis. For the integrity protection, the signature is calculated by the hardware implemented Lhash engine before the data sending off the chip, and the signature of the data block is recalculated and compared with the decrypted one at the load time. For the confidentiality protection, an AES encryption engine is used to generate the key stream, the plain data and the cipher data can translate through a simple XOR operation. The hardware cryptographic engines are optimized to work simultaneously with the memory access operation, which reduces the hardware overhead and the performance overhead. We implement the proposed architecture within OR1200 processor on Xilinx Virtex 5 FPGA platform. The experiment results show that the proposed hardware-enhanced protection method can preserve the integrity and confidentiality of the runtime data in the embedded systems with low power consumption and a marginal area footprint. The performance overhead is less than 2.27% according to the selected benchmarks.

Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.