At present, the embedded systems are facing various kinds of attacks, especially for the data stored in the external memories. This paper presents a hardware-enhanced protection method to protect the data integrity and confidentiality at runtime, preventing the data from spoofing attack, splicing attack, replay attack, and some malicious analysis. For the integrity protection, the signature is calculated by the hardware implemented Lhash engine before the data sending off the chip, and the signature of the data block is recalculated and compared with the decrypted one at the load time. For the confidentiality protection, an AES encryption engine is used to generate the key stream, the plain data and the cipher data can translate through a simple XOR operation. The hardware cryptographic engines are optimized to work simultaneously with the memory access operation, which reduces the hardware overhead and the performance overhead. We implement the proposed architecture within OR1200 processor on Xilinx Virtex 5 FPGA platform. The experiment results show that the proposed hardware-enhanced protection method can preserve the integrity and confidentiality of the runtime data in the embedded systems with low power consumption and a marginal area footprint. The performance overhead is less than 2.27% according to the selected benchmarks.

The growing prevalence of embedded systems in various applications has raised concerns about their vulnerability to malicious code reuse attacks. Current software-based and hardware-assisted security techniques struggle to detect or block these attacks with minor performance and implementation overhead. To address this issue, this paper presents a lightweight hardware-assisted scheme to enhance the security of embedded systems against code reuse attacks. We develop an on-chip lightweight hardware shadow stack to validate target addresses at runtime for backward-edge control flow integrity, which backs up valid return addresses during function calls and automatically verifies actual return addresses during the return phase. Additionally, we propose a lightweight stream cipher circuit that encrypts and decrypts critical stack data related to control flow manipulation, preventing attackers from analyzing or tampering with them. When designing and implementing the security mechanism for embedded systems, we fully consider the constraints of limited system resources and performance, optimizing both the architecture design and implementation of the proposed hardware. Finally, we integrate both the proposed lightweight hardware shadow stack and the runtime data encryption hardware into the OR1200 processor. We have verified the system security function on the Terasic DE1-SoC FPGA platform and evaluated the system performance as well as implementation overhead. The results show that the proposed lightweight hardware-assisted scheme can provide a dedicated defense capability against code reuse attacks for embedded systems, with an average system performance overhead of 0.39% and an area footprint of 0.316 mm².

Code reuse attacks (CRA) represent a type of control flow hijacking that attackers exploit to manipulate the standard program execution path, resulting in abnormal processor behaviors. In response to the security concern, proposals for Control Flow Integrity (CFI) verification have emerged. The CFI scheme diligently monitors program jumps during execution, effectively restraining abnormal program execution and robustly safeguarding against CRA. This paper provides a comprehensive analysis and synthesis of the current state of hardware-based CFI implementations. In this survey, we initially discuss common attack methods and variations of predominant CRA, elucidating the general procedural steps intrinsic to such attacks. We delve into the protective capacities inherent in contemporary hardware-based CFI implementations. By conducting a thorough examination and organization of diverse research endeavors on hardware-based CFI, we systematically classify CFI based on implementation methodologies, including label verification, instruction encryption, stack edge detection, instruction tracing, sensitive data isolation, and basic block validation. We provide comprehensive explanations and critical evaluations for each category followed by comparative analyses while offering personal insights on the evolution of hardware-based CFI.

The utilization of SPI-Flash in embedded systems is widespread, primarily serving as program storage during the boot process. As a result, the boot process is influenced to some extent by the SPI-Flash controller. This paper presents a lightweight SPI-Flash controller that simplifies the boot process design by establishing a direct connection between the SPI-Flash and AHB-lite bus interface, enabling rapid program execution in RAM instead of directly from the SPI-Flash. Additionally, the controller can function as a bare-metal program downloader for testing the boot process functionality during FPGA-based SoC (system-on-chip) prototype verification. The system-level simulation and FPGA verification results demonstrate that the proposed SPI-Flash controller successfully achieves its intended functional impact in operations to target the Micron N25Q256A SPI-Flash chip, boot process design, and bare-metal program download. The synthesis results under the SMIC 180 nm 1P8M technology process indicate that this SPI-Flash controller exhibits remarkable performance, power consumption, and area utilization. The source code of the proposed lightweight SPI-Flash controller has been uploaded to GitHub as an open-source project.

In this article, we report enhancing RF performance by improving the thermal management of gallium nitride (GaN) Schottky barrier diodes (SBDs), demonstrated through the application of a limiter. Benefiting from the rapid heat dissipation of microjet cooling, the impact of heat accumulation on the performance of GaN SBDs is analyzed, demonstrating the dependence of GaN lateral heterojunction devices on high thermal conductivity substrate. A GaN-SBD using high thermal conductivity SiC substrate was developed, reducing ON-resistance by 8% and improving saturation current by 12%. By combining microjet cooling with optimized substrates, the thermal management capability of GaN SBDs was significantly enhanced. RF performance was effectively evaluated using a passive limiter monolithic microwave integrated circuit (MMIC), showing the isolation was significantly improved by 3.5 dB at 80 W, and the reflected power was increased by 14%. The results highlight the improvements in RF performance achieved through enhanced thermal management of GaN SBDs and present a preliminary exploration of microjet cooling in high-power limiters.