One of the key technical challenges of the Google & IEEE Little Box competition, an international contest to build the world’s smallest 2kW single-phase inverter in 2015, was to shrink the volume of the energy storage required to cope with the twice mains-frequency (120 Hz) pulsating power at the AC side and meet the stringent 2:5% input voltage ripple at the DC side. In this paper, first, a full-power processing bucktype converter active buffer approach, selected by the 1st prize winner of the Little Box Challenge (LBC) is analyzed in detail. Being relieved from strict voltage ripple requirements, a larger voltage ripple is allowed across the buffer capacitor significantly reducing the capacitance requirement. Second, a partial-power active buffer approach, selected by the 2nd prize winner of the LBC, where conventional passive capacitive buffering of the DClink is combined with a series-connected auxiliary converter, used to compensate the remaining 120 Hz voltage ripple across the DClink capacitance, is studied in detail. In this paper, both selected concepts are comparatively evaluated in terms of achievable efficiency, power density and ripple compensation performance under both stationary and transient conditions. Novel control schemes and optimally designed hardware prototypes for both considered buffer concepts are presented and accompanied with experimental measurements to support the claimed efficiency and power density and assess the performance of the implemented control systems. Finally, by means of comparison with conventional passive DC-link buffering using only electrolytic capacitors, it is determined at what voltage ripple requirement it actually becomes beneficial in terms of volume to employ the considered active buffer concepts.

A design optimization of a generalized high step-up dc-dc converter applied as front-stage in a photovoltaic (PV) microinverter is proposed. The design methodology optimizes the weighted California Energy Commission (CEC) efficiency of the generalized converter considering not only the classical parameters, as turns ratio and switching frequency, but also the topology structure through different connections of voltage multiplier cells. Two design optimizations have been carried out. The first maximizes only the CEC efficiency, obtaining results around 98%. In the second it was added terms related to cost and volume in the objective function, which results in a converter with lower CEC efficiencies - around 96% - but with a higher power density and lower cost.

The next-generation industrial environment requires power supplies that are compact, efficient, low-cost, and ultra-reliable, even across mains failures, to power mission-critical electrified processes. Hold-up time requirements and the demand for ultra-high power density and minimum production costs, in particular, drive the need for power converters with (i) a wide input voltage range, to reduce the size of the hold-up capacitor, (ii) soft-switching over the full input voltage and load ranges, to achieve low losses that facilitate a compact realization, and (iii) complete PCB-integration for low-cost manufacturing. In this work, we conceptualize, design, model, fabricate, and characterize a $1.5$ $\mathrm{k}$$\mathrm{W}$, 12 $\mathrm{V}$-output DC/DC converter for industrial power supplies that is required to operate across a wide 300 $\mathrm{V}$–430 $\mathrm{V}$ input voltage range. This module utilizes an LLC-based control scheme for complete soft-switching and a snake-core transformer to divide the output current with a balanced flux among multiple secondary windings. Detailed loss models are derived for every component in the converter. The converter achieves close to 96% peak efficiency with a power density of 337 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($20.6$ $\mathrm{k}$$\mathrm{W}$/${\mathrm{d}\mathrm{m}}^{-3}$), excellent matching to the derived loss models, and zero-voltage switching even down to zero load. The loss models are used to identify improvements to further boost efficiency, the most important of which is the minimization of delay times in synchronous rectification, and a subsequent improved $1.5$ $\mathrm{k}$$\mathrm{W}$ hardware module eliminates nearly 25% of converter losses for a peak efficiency of nearly 97% with a power density of 308 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($18.8$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$). Two $1.5$ $\mathrm{k}$$\mathrm{W}$ modules are then paralleled to achieve 3 $\mathrm{k}$$\mathrm{W}$ output power at 12 $\mathrm{V}$ and 345 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($21.1$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$) with ideal current sharing between the secondary outputs and no drop in efficiency from a single module, an important characteristic enabled by the novel snake-core transformer.

This study aimed to present the design and field test results of an LED (light emitting diode) lamp for integrated pest management (IPM) and other entomological studies. The light spectrum of the LEDs was tuned to optimize insect attraction and lower energy consumption. An electronic circuit with control software was integrated with the lamp, enabling it to operate in standalone mode, automatically identify night and day, monitor and control the battery charge with energy from a photovoltaic solar panel, protect the battery against over-discharge, and provide feedback about the operating status of the system. Additionally, energy consumption is about five times lower than that of the fluorescent lamp, reducing the battery and solar panel size needed for its energy supply. In the 2017/2018 growing season, the smart LED lamp was installed in a Sonne light trap in an irrigated rice field, and the total number of insects captured was compared with the number collected in a conventional light trap fitted with a traditional 15 W black light fluorescent lamp. Total captures in the Sonne trap were approximately three times greater than in the conventional system.

Despite the increasing performance of power semi-conductors and passives components, limited timing resolution in off-the-shelf available digital control hardware often prevents the switching frequency in kW-scale dc/ac power conversion to be increased above several MHz for the sake of extreme power densities. In this paper an alternative approach to generate a sinusoidal output voltage, based on constant duty cycle frequency shift control of a high frequency resonant inverter stage and a subsequent synchronous cycloconverter, is analyzed. The design of the presented converter is facilitated by means of a derived mathematical model. A novel closed-loop control system is proposed which achieves tight regulation of the output voltage by means of controlling the switching frequencies of the involved bridge legs operated in resonant mode. Characteristic waveforms of the dc/ac converter during steady-state and load transients are presented. Two distinct implementations of the resonant inverter stage, constituting an intermediate voltage or intermediate current link, are analysed and compared.