In the past 20 years, NAND flash has un der gone dramatic scaling, with 2D NAND feature size going from 400 nm in 1998 to 15 nm in 2012 and 3D NAND increasing from 24 layers to 128 layers in just the past seven years. NAND density, expressed in terms of gigabits per square millimeter, has increased 100,000 times in the past 22 years [1]. Aside from physical scaling, NAND logical scaling has also undergone a transformation, evolving from singlelevel cell (SLC) to two bits per cell (MLC) to triplelevel cell (TLC) and now four bits per cell (QLC), which has been incorporated into many products. NAND die capacity has grown from 128 Mb in 2000 to 1.33 Tb in 2020.

Soft errors induced by high energy particles have been a severe concern in integrated circuits. Especially in advanced nanoscale technology nodes, the phenomenon of multi-node-upset caused by charge sharing is becoming a crucial issue. However, this problem remains a challenge as there are only few mitigation methods. This study demonstrates a cost-efficient latch named CROUT featuring double-node-upset tolerance. Integrating coupled Schmitt-triggers and four always-on high-threshold transistors, CROUT is highly reliable in the presence of double-node-upset. To further validate this, a test chip was fabricated in the 28nm CMOS process and tested in a heavy-ion radiation environment. The experimental results indicated that the radiation tolerance is about 2x higher than the standard latches. Moreover, compared to other state-of-the-art multi-node-upset tolerant latches, its power-delay-product (PDP) is reduced by 6x. The results show that our proposed latch is highly reliable and cost-effective for the space application, which further can be made into a standard cell to be integrated into large-scale circuits.

With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 $^\circ$ C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications.

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%<; area overhead <; 200%, the solutions of MIX have lower SER (SER reduction >81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft error issue in digital circuits. However, a multi-objective optimization (MOO) problem obviously appears when utilizing the hardened counterparts to replace the original unreliable cells. This paper proposes a MOO framework based on Bayesian Optimization (BO) for balancing design metrics like area, Longest Path Delay (LPD)/power, and Soft Error Rate (SER) while hardening digital circuits, including combinational and sequential circuits. This framework comprises two phases: 1) data preprocessing and 2) multi-objective Bayesian optimization. The first phase makes this framework much more applicable for large-scale circuits through data dimensionality reduction. The second phase is characterized by utilizing a black-box approach to greatly promote the efficiency and accuracy of MOO. Experimental results on benchmark circuits demonstrate that the framework achieves a 1.34x improvement in accuracy, an 11.47x enhancement in efficiency, and a 0.77x reduction in SER, while exhibiting a 4.27x and 0.72x increase in area for combinational and sequential benchmark circuits, respectively, along with a 0.54x increase in LPD and a 1.25x increase in power for Triple Modular Redundancy (TMR) techniques.

Emerging applications like deep neural networks require high off-chip memory bandwidth and low dynamic loaded Double Data Rate SDRAM (DDR) latency. However, under the stringent physical constraints of chip packages and system boards, it is extremely expensive to further increase the bandwidth and reduce the dynamic loaded latency of off-chip memory in terms of DDR devices. To address the latency issues in DDR subsystems, this paper presents a novel architecture aiming at achieving latency optimization through a use case sensitive controller. We propose a reevaluation of conventional decoupling mechanisms and quasi-static arbitration methods in the DDR scheduling architecture. The adaptive scheduling algorithms offer significant advantages in various real-world scenarios. The research methodology involves implementing a rank-level timing aware read/write turnaround arbiter and setting read/write queue thresholds and read/write turnaround settings based on observed patterns. By implementing the arbiter and dynamically adjusting these parameters, the proposed architecture aims to optimize the performance of the DDR subsystem. To validate the effectiveness of the architecture, we conduct multiple experiments. These experiments evaluate the performance of the DDR subsystem under various workloads and configurations. The results demonstrate that the adaptive scheduling algorithms have advantages in achieving DDR performance attributes for workloads and improving system performance. The experimental results provide evidence of the architecture’s effectiveness in reducing latency by around 10% to 50% in various real-world scenarios.