Soft errors induced by high energy particles have been a severe concern in integrated circuits. Especially in advanced nanoscale technology nodes, the phenomenon of multi-node-upset caused by charge sharing is becoming a crucial issue. However, this problem remains a challenge as there are only few mitigation methods. This study demonstrates a cost-efficient latch named CROUT featuring double-node-upset tolerance. Integrating coupled Schmitt-triggers and four always-on high-threshold transistors, CROUT is highly reliable in the presence of double-node-upset. To further validate this, a test chip was fabricated in the 28nm CMOS process and tested in a heavy-ion radiation environment. The experimental results indicated that the radiation tolerance is about 2x higher than the standard latches. Moreover, compared to other state-of-the-art multi-node-upset tolerant latches, its power-delay-product (PDP) is reduced by 6x. The results show that our proposed latch is highly reliable and cost-effective for the space application, which further can be made into a standard cell to be integrated into large-scale circuits.

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( $C_P$ ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- $\mu$ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 $\times$ . In addition, with the four $C_P$ serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of $>$ 3.5 $\times$ can be maintained with a PEH input voltage from 0.78 to 4.9 V.

While attention-based approaches have shown considerable progress in enhancing image fusion and addressing the challenges posed by long-range feature dependencies, their efficacy in capturing local features is compromised by the lack of diverse receptive field extraction techniques. To overcome the shortcomings of existing fusion methods in extracting multi-scale local features and preserving global features, this paper proposes a novel cross-modal image fusion approach based on a multi-scale convolutional neural network with attention Transformer (MATCNN). MATCNN utilizes the multi-scale fusion module (MSFM) to extract local features at different scales and employs the global feature extraction module (GFEM) to extract global features. Combining the two reduces the loss of detail features and improves the ability of global feature representation. Simultaneously, an information mask is used to label pertinent details within the images, aiming to enhance the proportion of preserving significant information in infrared images and background textures in visible images in fused images. Subsequently, a novel optimization algorithm is developed, leveraging the mask to guide feature extraction through the integration of content, structural similarity index measurement, and global feature loss. Quantitative and qualitative evaluations are conducted across various datasets, revealing that MATCNN effectively highlights infrared salient targets, preserves additional details in visible images, and achieves better fusion results for cross-modal images. The code of MATCNN will be available at https://github.com/zhang3849/MATCNN.git.

High Efficiency Video Coding (HEVC), the latest video coding standard, aims to provide coding performance that is much superior to that of its predecessor, H.264, especially for high definition video. To fulfill this goal, the inter-prediction unit (PU) partitions of HEVC are more complex, and the search range of motion estimation (ME) is much larger. As a result, ME becomes a bottleneck in the design of the HEVC inter predictor. In response to this challenge, we developed a hardware-oriented integer ME algorithm and the related hardware implementation. Our proposed algorithm led to a decrease in terms of the Bjontegaard Delta rate when compared with the HEVC test model 15.0. The corresponding hardware solution benefitted from 2-D data reuse supported by horizontal and vertical reference SRAMs, on-chip memory reduction supported by 4 × 4 block compression, and a low-power sum of absolute difference (SAD) tree supported by PU-level chip selection. When adopting a 32 × 32 SAD tree, the minimum and maximum required working frequency for 4K × 2K at 30 frames/s videos was [375, 500] MHz. These results demonstrated that our proposed solution offered desirable improvement in both coding speed and coding performance.

This brief presents a tutorial on multifaceted techniques for high efficiency piezoelectric energy harvesting. For the purpose of helping design piezoelectric energy harvesting system according to different application scenarios, we summarize and discuss the recent design trends and challenges. We divide the design focus into the following three categories, namely, (1) AC-DC rectifiers, (2) C_P compensation circuits, (3) maximum power point tracking (MPPT) circuits. The features, problems encountered, and suitable systems of various AC-DC rectifier topologies are introduced and compared. The important role of non-linear methods for piezoelectric energy harvesting is illustrated from the perspective of impedance matching. Energy extraction techniques and voltage flipping techniques based on inductors, capacitors, and hybrid structures are analyzed. MPPT techniques with different features and targets are discussed.

Simultaneous localization and mapping (SLAM), a pivotal technology in robotics, autonomous vehicles, and surveillance, has gained prominence with the emergence of edge intelligence. Developing energy-efficient, low-latency SLAM systems is essential due to resource constraints and real-time demands. Compute-in-memory (CIM) architectures have been proven to be efficient for matrix multiplications. However, applications for SLAM raise new challenges in memory access and computation aspects: the linear system solving (LS) requires row transformation and causes frequent CIM updates, while the backend optimization causes redundant memory access; back-end optimization dominates SLAM’s computation and requires high precision and high dynamic range. Thus, we propose SLAM-CIM, a visual SLAM backend processor for edge robotics. A dynamic-range-driven-skipping CIM macro is designed to realize energy-efficient floating point (FP)-multiply-and-accumulate (MAC) operations. A preconditional-conjugate-gradient-based in-memory linear solver (PILARS) is designed to achieve LS without additional row transformations. This reduces memory access by $2.08{\times }$ and linear-system-solving latency by $3.84{\times }$ . SLAM-CIM further minimizes CIM weight updates through incremental bundle adjustment (BA), increasing average CIM utilization by $2.8{\times }$ . A silicon prototype is fabricated using 28-nm CMOS technology. The measurements show that SLAM-CIM achieves accurate and efficient SLAM operations with an average energy efficiency of 31.53 TFLOPS/W.