Quantum well solar cells, as a promising approach for next-generation photovoltaic technology, have received great attention in the last few years. Recent developments in materials growth and device structures of quantum wells have opened up new avenues for the incorporation of quantum well structures in next-generation III/V multi-junction solar cells. In this paper, the advantages and challenges of growing quantum wells in the unintentionally doped (i) region of p-i-n solar cells are reviewed. We focus on the recent progress in 1.1–1.3 eV strain-balanced InGaAs/GaAsP, 1.6–1.8 eV strain-balanced and lattice-matched InGaAsP/InGaP, and >2.1 eV strained InGaN/GaN quantum well solar cells, including optimization of the quantum well growth conditions and improving the solar cell structure. For each material system, the challenges associated with materials growth and device performance such as critical layer thickness constraints, strain balance, bandgap tunability, and carrier transport limitations, are discussed. The performance of each quantum well solar cell is compared with bulk absorber operating in the same bandgap range, with the advantages of each being highlighted. The effect of the unintentional background doping on carrier collection (by drift) is presented through modeling and recent experimental results. The recent strategies to enhance the electric field distribution across the quantum well region are reviewed. The potential of incorporating quantum well structures in next-generation multi-junction devices is also discussed.

In this Letter, a series of metal-insulator-semiconductor capacitors consisting of Si₃N₄ dielectrics with different thicknesses on GaN have been fabricated to investigate their interface states. The measurement value extracted from ultraviolet assisted capacitance-voltage methods can be explained by the existence of spatially uniform hole traps in Si₃N₄. An improved model combining the effects from interface states and hole traps in Si₃N₄ is proposed to extract the interface state density ($D_{it}$ ) accurately. Based on the model, $D_{it}$ can be obtained by extrapolating the trap density to a zero-thickness dielectric. The extracted average $D_{it}$ value of the Si₃N₄/GaN interface is ∼3.8 × 10¹¹ cm⁻²eV⁻¹, and the hole trap concentration in Si₃N₄ is ∼3.1 × 10¹⁸ cm⁻³. The results, model, and analysis presented here provide new insights into studying $D_{it}$ of various dielectrics on GaN and other wide-bandgap semiconductors.

UV-assisted capacitance–voltage (C–V) and current–voltage (I–V) measurements were performed on ∼20 nm HfO₂/GaN metal–insulator–semiconductor capacitors. The effects of surface preparation, predeposition treatment, HfO₂ deposition process, and post-deposition annealing environment on interface characteristics were studied. Surface preparation by etching in diluted BHF and piranha etch prior to atomic layer deposition (ALD) suppressed the interface states compared to the baseline sample possibly due to the removal of the native oxide and impurities. UV/ozone treatment prior to HfO₂ deposition reduced the interface states by one order of magnitude compared to the baseline sample possibly due to the formation of a thin Ga₂O₃ interlayer. In situ ALD pretreatment with tri-methyl-aluminum/N₂ plasma was also found to reduce the surface states significantly compared to the baseline sample. In addition, thermal ALD improved the dielectric constant and breakdown voltage of the dielectric as compared to plasma ALD due to less surface damage. The lowest average interface trap density achieved was 1.64 × 10¹² cm⁻²/eV with an HfO₂ dielectric constant of 16 on the sample with UV/ozone and piranha treatment with in situ ALD treatment and thermal ALD deposition.

The interface and bulk properties of aluminum-silicon-oxide (AlSiO) dielectric grown by metal-organic chemical vapor deposition (MOCVD) on (001) β-Ga₂O₃ were investigated systematically using a deep UV-assisted capacitance–voltage methodology. The improved surface preparation with a combination of UV-ozone and wet chemical treatment reduced near-interface traps resulting in a negligible hysteresis. An average interface state density of 6.63 × 10¹¹ cm⁻²eV⁻¹ and AlSiO bulk trap density of 4.65 × 10¹⁷ cm⁻³eV⁻¹ were quantified, which is half of that for Al₂O₃ deposited by atomic layer deposition (ALD). A net positive interface fixed charge of 1.56 × 10¹² cm⁻² was measured. In addition, a high dielectric breakdown field of ∼7.8 MV/cm and more effective suppression of gate leakage were achieved on these devices compared with ALD-Al₂O₃ on similar metal-oxide-semiconductor (MOS) structures.

The electrical properties and trapping characteristics of Si₃N₄ and SiO₂ dielectrics grown in situ on (000-1) N-polar GaN by metal organic chemical vapor deposition are investigated in this paper. The fixed charges, densities of near-interface trap states, and interface trap density in N-polar Si₃N₄ and SiO₂ metal insulator semiconductor capacitors (MISCAPs) are quantified using a capacitance-voltage measurement method which is assisted by ultraviolet illumination and applied voltage-stress. The fixed charges and trap states are located at or near the interface of Si₃N₄ (SiO₂)/N-polar GaN as indicated by the linear relationship between the flatband voltage/hysteresis and the Si₃N₄ (SiO₂) thickness. Positive flatband voltages were measured for both the N-polar Si₃N₄ and SiO₂ MISCAPs which is a promising route toward realizing normally off GaN-based metal insulator semiconductor power devices. Net negative fixed charge densities of 2.9 × 10¹² cm⁻² and 3.3 × 10¹² cm⁻² are located at the interface of Si₃N₄/GaN (N-polar) and SiO₂/GaN (N-polar), respectively. The origin of this net negative interface fixed charge is briefly discussed, and the trap densities with fast and slow emission rates are quantified in both the N-polar Si₃N₄ and SiO₂ MISCAPs. This study is a step toward identifying suitable gate dielectrics that can be integrated into N-polar high electron mobility transistors for high-frequency and switching applications.

The electrical properties and the interface abruptness of aluminum silicon oxide (AlSiO) dielectric grown in situ on $\left(000\overline{1}\right)$ N-polar and (0001) Ga-polar GaN by metal organic chemical vapor deposition were studied by means of capacitance-voltage (CV) and atom probe tomography (APT) measurements. The growth of AlSiO on N-polar GaN resulted in a positive flatband voltage shift of 2.27 V with respect to that on Ga-polar GaN, which exemplifies the influence of the GaN surface polarization charge on the electrical properties of GaN-based metal oxide semiconductor (MOS) devices. The AlSiO/GaN(N-polar) interface was sharp, which resulted in nondispersive CV characteristics and a relatively low density of interface states (D_it) of 1.48 × 10¹² cm⁻². An intermixed layer of AlGaSiO was present at the interface between AlSiO and Ga-polar GaN, which contributed to the measured dispersive CV characteristics and resulted in an ∼2× higher D_it than that on N-polar GaN. The superior properties of the N-polar AlSiO MOS devices are promising for further advancement of N-polar GaN-based high electron mobility transistors for high-frequency and power electronics applications.