In this paper, a Ni-Al alloy based metal induced lateral crystallization (MILC) process in a vertical Si channel, from 3-D NAND flash cell, is reported. Alloying Ni with Al improves NiSi2 nucleation, resulting in a favorable channel morphology after the silicide transport. We show that it is possible to achieve better ON-current and gate control over the existing Ni-only MILC process with no observable impact on the memory performance.

In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity (ρ_C) values are 1.6 × 10⁻⁵ Ω cm² (Mo) and 4.2 × 10⁻⁶ Ω cm² (Pd) for a doping level of 1 × 10¹⁹ cm⁻³. An apparent dependence of ρ_C on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO₂ interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

3-D NAND Flash has become the workhorse for non-volatile memory based storage. It is evermore important to develop solutions that keep NAND scaling in a sustainable path with respect to cost and performance. The memory cells in 3-D NAND are addressed by horizontal word lines (WLs) that are stacked vertically. With each technology node, the WL metallization, performed using CVD/ALD tungsten metal with a thin TiN barrier, poses a challenge in terms of WL cavity filling and WL resistance. A wet nickel boron (NiB) electroless and barrierless deposition is proposed for the next generation 3-D NAND Flash technology. Here, we investigate the memory behavior using metal/high-k/ONO/Si (MHONOS) capacitors while the resistivity and tensile stress were studied on blankets. Results indicate that the program and erase performance of the NiB devices are comparable to that of the W/TiN reference. Furthermore, the tensile stress is two times lower for the NiB integration.

2023 International Conference on Solid State Devices and Materials ,Polysilicon channel in 3-D NAND: Challenges and Strategies for Improvement