We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating pulse; hence, the length ratio of the lines determines the pulse-shrinking capability of the converter. This resolution control mechanism is different from the bias adjustment typically used in complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) pulse-shrinking elements. Two forms of representation of a measured time interval (the pulse width and the time interval between two pulses) are utilized in the described converter to improve the efficiency of resolution control. To diminish the jitter of the edges of a circulating pulse and, consequently, to increase the precision of the converter, a two-stage conversion is introduced. The first stage, having a low resolution, rapidly shortens the measured pulse, thus limiting the number of cycles, whereas the second stage provides a final high resolution within a narrow time interval range. The optimal resolution of the first conversion stage is theoretically derived. Mostly, the same logical resources of the FPGA device are utilized in both conversion stages; thus, the overall area overhead of the converter is reduced. The converter has a resolution of 42 ps and a measurement uncertainty of below 56 ps within the measurement range of 11.5 ns. The converter has been implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx).

This paper presents two principles that make multiple time coding lines-based time-to-digital converter implementation in FPGA device more efficient. A pseudo-segmented delay line allows for saving many logical resources by effective utilization of programmable logic block elements. A chopped time coding line improves measurement resolution and precision and takes advantage of a global clock network skew. Both designs were implemented in Kintex-7 FPGA chip, manufactured by Xilinx in 28 nm CMOS process, and compared to well-known time coding line solutions, i.e. a commonly used “plain” architecture and a tuned delay line. All four designs, working in a single and multiply configurations, were tested and compared in terms of resource utilization, measurement resolution and precision. Designed time-to-digital converters employed in a one channel timestamps-based interpolating time counter allowed to get mean resolution of 1 ps and precision even below 4 ps using up to ten time coding lines.