This paper presents two principles that make multiple time coding lines-based time-to-digital converter implementation in FPGA device more efficient. A pseudo-segmented delay line allows for saving many logical resources by effective utilization of programmable logic block elements. A chopped time coding line improves measurement resolution and precision and takes advantage of a global clock network skew. Both designs were implemented in Kintex-7 FPGA chip, manufactured by Xilinx in 28 nm CMOS process, and compared to well-known time coding line solutions, i.e. a commonly used “plain” architecture and a tuned delay line. All four designs, working in a single and multiply configurations, were tested and compared in terms of resource utilization, measurement resolution and precision. Designed time-to-digital converters employed in a one channel timestamps-based interpolating time counter allowed to get mean resolution of 1 ps and precision even below 4 ps using up to ten time coding lines.

We present the design, operation, and test results of a new integrated time interval (TI) counter that provides high resolution (1.9 ps), low measurement uncertainty (below 4.5-ps rms in advanced measurement modes), and wide measurement range (above 1 h, easily extendable). Fundamental for the counter, TI measurements are simultaneously performed in eight independent channels, while the advanced configuration of input channels improves either the precision (up to 3 ps) or the measurement speed (up to 91.2 × 10 ⁶ registered events/s). The functional flexibility and high speed are achieved based on the timestamp (TS) principle that makes possible registering on the common time scale events appearing at counter inputs and then measuring the time intervals between any registered events. The high precision is obtained by employing two-stage inner interpolation with an eight-phase clock in the first stage of interpolation and an equivalent time coding delay line in the second one. The time counter is integrated in a single, costeffective field programmable gate array chip manufactured in a 28-nm CMOS process.

This paper presents the design, implementation, and test results of a multichannel time interval and frequency counter developed as a desktop instrument. The counter contains four main functional modules for (1) performing precise measurements, (2) controlling and fast data processing, (3) low-noise power suppling, and (4) supplying a stable reference clock (optional rubidium standard). A fundamental for the counter, the time interval measurement is based on time stamping combined with a period counting and in-period two-stage time interpolation that allows us to achieve wide measurement range (above 1 h), high precision (even better than 4.5 ps), and high measurement speed (up to 91.2 × 10⁶ timestamps/s). The frequency is measured up to 3.0 GHz with the use of the reciprocal method. Wide functionality of the counter includes also the evaluation of frequency stability of clocks and oscillators (Allan deviation) and phase variation (time interval error, maximum time interval error, time deviation). The 8-channel measurement module is based on a field programmable gate array device, while the control unit involves a microcontroller with a high performance ARM-Cortex core. An efficient and user-friendly control of the counter is provided either locally, through the built-in keypad or/and color touch panel, or remotely, with the aid of USB, Ethernet, RS232C, or RS485 interfaces.

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

The quantization error in interpolating time counters is analyzed for three models of interpolator and for correlated and uncorrelated input events representing the start and end of the measured time interval. The analysis is related to the currently most common two-stage time interpolation method and based on data from several up-to-date integrated time counters. The main aim of this discussion is to find a general and accurate method for presentation and calculation of the quantization error in real, non-ideal time counters. We propose a novel graphical representation of the error, which may be useful for analysis of time counters with any interpolation method used.