A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying a binary-weighted searching algorithm at the first A/D conversion attempt. By effectively reducing the reference signal range, the proposed FHR readout scheme can reduce the number of A/D conversion steps in the SS ADC while maintaining the ADC performance. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed FHR scheme becomes more effective as the bit-depth of the ADC increases. A prototype CIS with a column-parallel 11-bit SS ADC was fabricated in a 0.11-μm 1P4M CIS process with a 2.9-μm pixel pitch. A maximum frame rate of 570 frames/s was achieved with a 1024×240 pixel resolution, corresponding to a 140.08 Mp/s pixel rate. Total power consumption was 57.2 mW under 2.8 V for pixel readout and 1.8 V for readout circuitry. When compared with the conventional 11-bit SS ADC, the proposed FHR scheme shortens the total A/D conversion time by 38.4%. The prototype CIS demonstrated the figure of merits (FoM) of 0.84 e ^- ·nJ and 0.41 e ^- ·nJ/step.

This paper presents a real-time edge image extraction CMOS image sensor (CIS) with an edge detection counter for machine vision applications. By examining a conventional column-parallel CIS imaging structure with a single-slope analog-to-digital convertor, it discovered an additional time slot available to extract information of an additional image during a normal imaging operation of two adjacent columns. While obtaining a normal image in this study, the prototype CIS with the proposed edge detection counter effectively utilizes the spare time for extracting an additional column edge image without an image signal processor and any computational latency. In addition, by applying a proposed variable edge thresholding function, the proposed CIS can adopt an optimum edge threshold value according to its imaging condition, alleviating an inherent limitation of a column edge image. This prototype CIS was fabricated using a 0.18-μm 1P6M CMOS process with an effective pixel resolution of 320 (H) × 320 (V). The prototype consumes 17.72 mW power with a frame rate of 240 frames per second. The prototype CIS demonstrated a figure of merit of 721 pW/frame pixel.

This study presents a CMOS image sensor (CIS) with a two-step single-slope (TS-SS) analog-to-digital convertor (ADC), wherein the differential topology characteristics of a ramp generator are used. The proposed TS-SS ADC effectively resolves 1 most significant bit (MSB) with a half-ramping of a full analog-to-digital (A/D) reference at coarse conversion and the remaining least significant bits (LSBs) with differential slope ramping signals from the ramp generator. The proposed readout scheme maintains the existing column readout structure and does not require to regenerate the coarse-step region in each column. Moreover, the proposed TS-SS readout scheme is verified for a frame rate enhancement, that is, the efficiency increases as the bit depth of the ADC increases. A prototype CIS with the proposed 10-bit TS-SS ADC was implemented in a 1P4M 0.11- $\mu \text{m}$ CIS process with a 2.9- $\mu \text{m}$ pitch. The measurement results of the prototype CIS demonstrated the figure of merits (FoMs) of $102~\mu \text{V}\cdot $ pJ/steps and $2.79~\mu \text{V}$ /MHz/steps.

Based on an analysis of the signal characteristics of gas sensors, this work presents a chemoresistive sensor readout circuit design for detecting gases with slow response time characteristics. The proposed readout circuit directly generates a reference voltage corresponding to the initial value of the gas sensor and extracts only the amount of gas concentration change in the sensor. Because the proposed readout circuit can adaptively regenerate the suitable reference voltage under various changing ambient conditions, it can alleviate the variation in output values at the same gas concentration caused by non-uniformities among gas sensors. Furthermore, this readout circuit effectively eliminates the initial value shifts due to the poor reproducibility of the gas sensor itself without requiring complex digital signal calibrations. This work focuses on a commercially viable readout circuit structure that can effectively obtain slow response gas information without requiring a large capacitor. The proposed readout circuit operation was verified by simulations using spectre in cadence simulation software. It was then implemented on a printed circuit board with discrete components to confirm the effectiveness with existing gas sensor systems and its commercial viability.

This article presents a black-sun readout scheme for CMOS image sensors (CISs) that utilizes the black-sun effect caused by a strong illumination condition. Based on the analysis of the black-sun phenomenon in CISs, the proposed CIS extracts the black-sun indication and its strength images while providing normal images without any degradation. By effectively utilizing the black-sun readout capability, a prototype CIS with the proposed readout scheme was identified as a useful solution to track the brightest source of light. In addition, the proposed black-sun readout scheme is reversible to the conventional readout scheme such that it can be used for various purposes in several electronic devices using CISs. The proposed readout scheme was verified in the typical CIS structure, and it shows the feasibility of utilizing it in sun tracking sensor applications for improving energy conversion efficiency. The prototype chip was implemented in a 0.11-μm 1P4M CIS process with a 2.9-μm pitch.

This letter presents a wide dynamic range (WDR) feature extraction (FE) readout scheme for machine vision applications using CMOS image sensors (CISs). The proposed scheme with the proposed pixel structure has two operating modes, the normal and WDR modes. In the normal operating mode, the proposed CIS captures a normal image with high sensitivity. In addition, as a unique function, a bi‐level image is obtained for real‐time FE even if a pixel is saturated in strong illumination conditions. Thus, compared to typical CISs for machine vison, the proposed CIS can reveal object features that are blocked by light in real time. In the WDR operating mode, the proposed CIS produces a WDR image with its corresponding bi‐level image. A prototype CIS was fabricated using a standard 0.35‐μm 2P4M CMOS process with a 320 × 240 format (QVGA) with 10‐μm pitch pixels. At 60 fps, the measured power consumption was 5.98 mW at 3.3 V for pixel readout and 2.8 V for readout circuitry. The dynamic range of 73.1 dB was achieved in the WDR operating mode.