We report an area- and energy-efficient integrated circuit architecture of a 128-channel Δ-modulated Δ Σ analog front-end (Δ-Δ Σ AFE) for 1024-channel 3-D massive-parallel neural recording microsystems. Our platform has adopted a modularity of 128 channels and consists of eight multi-shank neural probes connected to individual AFEs through interposers in a small form factor. In order to reduce both area and energy consumption in the recording circuits, we implemented a spectrum equalization scheme to take advantage of the inherent spectral characteristics of neural signals, where most of the energy is confined in low frequencies and follows a ~1/f curve in the spectrum. This allows us to implement the AFE with a relaxed dynamic range by ~30 dB, thereby contributing to the significant reduction of both energy and area without sacrificing signal integrity. The Δ -Δ Σ AFE was fabricated using 0.18-μm CMOS processes. The single-channel AFE consumes 3.05 μW from 0.5 and 1.0 V supplies in an area of 0.05 mm² with 63.8-dB signal-to-noise-and-distortion ratio, 3.02 noise efficiency factor (NEF), and 4.56 NEF²VDD. We also have achieved an energy-area product, a figure-of-merit most critical for massive-parallel neural recording systems, of 6.34 fJ/C·s·,mm².

We report a scalable neural recording interface with embedded lossless compression to reduce dynamic power consumption (P _D ) for data transmission in high-density neural recording systems. We investigated the characteristics of neural signals and implemented effective lossless compression for local field potential (LFP) and extracellular action potential (EAP or spike) in separate signal paths. For LFP, spatial- temporal (spatiotemporal) correlation of the LFP signals is exploited in a A-modulated AΣ analog-to-digital converter (A - AΣ ADC) and a dedicated digital difference circuit. Then, statistical redundancy is further eliminated through entropy encoding without information loss. For spikes, only essential parts of waveforms in the spikes are extracted from the raw data by using spike detectors and reconfigurable analog memories. The prototype chip was fabricated using 180-nm CMOS processes, incorporating 128 channels into a modular architecture that is easily scalable and expandable for high-density neural recordings. The fabricated chip achieved the data rate reduction for the LFPs and spikes by a factor of 5.35 and 10.54, respectively, from the proposed compression scheme. Consequently, P _D was reduced by 89%, when compared to the uncompressed case. We also achieved the state-of-the-art recording performance of 3.37 μW per channel, 5.18 μV _rms noise, and 3.41 NEF ² V _DD .

We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm2 footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 m. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 W from 1.2 V and 1.8 V supplies in an area of 0.0161 mm2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 Vrms input-referred noise from 0.5 Hz to 10 kHz, and 48 M input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.

This study presents a CMOS image sensor (CIS) with a two-step single-slope (TS-SS) analog-to-digital convertor (ADC), wherein the differential topology characteristics of a ramp generator are used. The proposed TS-SS ADC effectively resolves 1 most significant bit (MSB) with a half-ramping of a full analog-to-digital (A/D) reference at coarse conversion and the remaining least significant bits (LSBs) with differential slope ramping signals from the ramp generator. The proposed readout scheme maintains the existing column readout structure and does not require to regenerate the coarse-step region in each column. Moreover, the proposed TS-SS readout scheme is verified for a frame rate enhancement, that is, the efficiency increases as the bit depth of the ADC increases. A prototype CIS with the proposed 10-bit TS-SS ADC was implemented in a 1P4M 0.11- $\mu \text{m}$ CIS process with a 2.9- $\mu \text{m}$ pitch. The measurement results of the prototype CIS demonstrated the figure of merits (FoMs) of $102~\mu \text{V}\cdot $ pJ/steps and $2.79~\mu \text{V}$ /MHz/steps.

In this paper, we present a low-power, low-noise fully differential pseudo-open-loop preamplifier with programmable bandwidth for monitoring neural activities. The proposed pseudo-open-loop topology can achieve high-power-noise efficiency as well as high linearity and precise gain control over process. The proposed fully differential preamplifier can balance the common mode of the differential outputs without a commonmode feedback circuit, and bias the ac-coupled input transistors without an external reference. A current-ratio gain design can set a stable gain over process and bias current variations. A programmable embedded g _m - C low-pass filter (LPF) can be tuned by adjusting bias current, so that the proposed preamplifier can be configured to be used in recording single neuron spikes or field potentials (EEG, ECoG). The proposed amplifier is configured to consume 400 nA at 2.5-V power supply; the total chip area is 0.189 mm ² . The measured thermal noise floor is 85 nV/√Hz and input-referred noise is 1.69 μV _rms from 0.3 Hz to 1 kHz when using a chopper stabilization technique to suppress 1/f noise. The fabricated preamplifier shows a noise efficiency factor of 2.43 in the fully differential topology.

We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66ms∙nJ/pixel with digital backend processing.