This paper presents new Built-In Self-Test (BIST) schemes for fault detection and diagnosis of Basic Logic Element (BLE) and intra-cluster (local) interconnect of a novel mesh of cluster FPGA. The proposed schemes avoid redundant test/diagnosis configurations by merging multiple configurations without losing diagnostic resolution. Efficiency of these schemes is calculated in terms of respective number of test/diagnosis configurations for the new FPGA. Results show that 50 BIST configurations are required for a complete test and diagnosis of the cluster. The testability aspects of this FPGA are explored in comparison with the classic clustered-mesh FPGA of the same parameters.

FPGA undergoes a large number of test configurations for faults detection and diagnosis which requires a significant amount of test time and off-chip memory to store test configuration bits. Some FPGAs support partial reconfiguration in which a portion of FPGA can be reconfigured without reconfiguring the remaining portions. This partial reconfiguration approach can be utilized for FPGA testing, to reduce the amount of test time and configuration bit storage. In this paper, we propose a Built-In Self-test (BIST) scheme utilizing partial reconfigurability of a mesh FPGA. To implement the BIST scheme, automated tools are developed to produce the required configuration bitstream using standard FPGA CAD flow. A comparative analysis of partial and full reconfiguration is presented which shows that test time and storage size for configuration bitstream reduce to half using partial reconfiguration approach.

This paper describes the design principles of a software based on-line testing application used to monitor manycore architectures running multi thread functional applications. The key idea is to have a non intrusive monitoring application running in parallel with the functional one. The monitoring application aims at detecting and reacting to software or hardware malfunctions, and can be seen as a service provided by the operating system. This monitoring method relies on the use of embedded sensors that capture physical values (temperature, ...) from the chip, or software-related indicators like CPU load. A case-study implementing this methodology has been performed and results in terms of memory usage and performance overhead are given.

Using standard Floating-Point (FP) formats for computation leads to significant hardware overhead since these formats are over-designed for error-resilient workloads such as iterative algorithms. Hence, hardware FP Unit (FPU) architectures need run-time variable precision capabilities. In this work, we propose a new method and an FPU architecture that enable designers to dynamically tune FP computations’ precision automatically at run-time called Variable Precision in Time (VPT), leading to significant power consumption, execution time, and energy savings. In spite of its circuit area overhead, the proposed approach simplifies the integration of variable precision in existing software workloads at any level of the software stack (OS, RTOS, or application-level): it only requires lightweight software support and solely relies on traditional assembly instructions, without the need for a specialized compiler or custom instructions. We apply the technique on the Jacobi and the Gauss–Seidel iterative methods taking full advantage of the suggested FPU. For each algorithm, two modified versions are proposed: a conservative version and a relaxed one. Both algorithms are analyzed and compared statistically to understand the effects of VPT on iterative applications. The implementations demonstrate up to 70.67% power consumption saving, up to 59.80% execution time saving, and up to 88.20% total energy saving w.r.t the reference double precision implementation, and with no accuracy loss.

Neural networks (NNs) are increasingly used in embedded systems driven by artificial intelligence (AI) features. Such systems are now developed for many critical applications with strong dependability constraints and trustworthiness requirements. The effect of bit-flips occurring during inferences in the field has therefore become a major concern. Dedicated design methods have been proposed to increase the robustness of NNs and enforce trustworthiness, while minimizing implementation overheads in the context of Edge AI. Such approaches are usually based on criticality criteria characterizing the most impactful bit-flips. In this work, the two main criteria are revisited in the case of bit-flips in data that is independent of the hardware/software implementation. Extensive statistical fault injection results are analyzed for a case study based on a quantized version of LeNet. They first demonstrate that any criterion is only held in some perturbation conditions, depending on the type of perturbed data and on the perturbed layer. The data representation format has also a significant impact. Surprising outcomes of the case study allow identifying a new parameter overlooked in the literature, i.e., the definition of the activation functions. Another important finding, mostly neglected in the literature, is the large number of bit-flips having a positive impact on inferences by correcting misclassifications of the nominal NN. In the presented case study, almost 40% of the misclassifications due to bit-flips are compensated for by the positive effects of other bit-flips, leading to only 0.06% global accuracy loss when bit-flips occur. These outcomes indicate that mitigations must be carefully tailored to each layer and data subset of the NN in order to accurately limit the effect of critical bit-flips. Moreover, at the same time they must avoid suppressing the advantage taken from bit-flips with positive effects. Although derived from a specific case study, these findings have a wide significance in design practice.