Ahmed Kira

Mr. Ahmed Kira


Research Focus & Metrics

Academic Career Length

6Years (2021-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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29 October 2021 in Electronics
Verified
Journal Article
Open access
PDF file
AKAhmed Kira
Ahmed Kira
MEMohannad Elsayed
Mohannad Elsayed
KAKarim Allidina
Karim Allidina
Vamsy ChodavarapuVamsy Chodavarapu
Vamsy Chodavarapu
MEMourad N. El-Gamal
Mourad N. El-Gamal
This article presents a 6.89 MHz MEMS oscillator based on an ultra-low-power, low-noise, tunable gain/duty-cycle transimpedance amplifier (TIA) and a bulk Lamé-mode MEMS resonator that has a quality factor (Q) of 3.24 × 106. Self-cascoding and current-starving techniques are used in the TIA design to minimize the power consumption and tune the duty-cycle of the output signal. The TIA was designed and fabricated in TSMC 65 nm CMOS process technology. Its open-loop performance has been measured separately. It achieves a tunable gain between 107.9 dBΩ and 118.1 dBΩ while dissipating only 143 nW from a 1 V supply. The duty-cycle of the output waveform can be tuned from 23.25% to 79.03%. The TIA has been interfaced and wire bonded in a series-resonant oscillator configuration with the MEMS resonator and mounted in a small cavity standard package. The closed-loop performance of the whole oscillator has been experimentally measured. It exhibits a phase noise of −128.1 dBc/Hz and −133.7 dBc/Hz at 1 kHz and 1 MHz offsets, respectively.

13 December 2024 in Sensors
Verified
Journal Article
Open access
PDF file
AKAhmed Kira
Ahmed Kira
MEMohannad Elsayed
Mohannad Elsayed
KAKarim Allidina
Karim Allidina
Vamsy ChodavarapuVamsy Chodavarapu
Vamsy Chodavarapu
MEMourad N. El-Gamal
Mourad N. El-Gamal
This article reports a 110.2 MHz ultra-low-power phase-locked loop (PLL) for MEMS timing/frequency reference oscillator applications. It utilizes a 6.89 MHz MEMS-based oscillator as an input reference. An ultra-low-power, high-resolution phase-frequency detector (PFD) is utilized to achieve low-noise performance. Eliminating the reset feedback path used in conventional PFDs leads to dead/blind zone-free phase characteristics, which are crucial for low-noise applications within a wide operating frequency range. The PFD operates up to 2.5 GHz and achieves a linear resolution of 100 ps input time difference (Δtin), without the need for any additional calibration circuits. The linearity of the proposed PFD is tested over a phase difference corresponding to aa Δtin ranging from 100 ps to 50 ns. At a 1 V supply voltage, it shows an error of <±1.6% with a resolution of 100 ps and a frequency-normalized power consumption (Pn) of 0.106 pW/Hz. The PLL is designed and fabricated using a TSMC 65 nm CMOS process instrument and interfaced with the MEMS-based oscillator. The system reports phase noises of −106.21 dBc/Hz and −135.36 dBc/Hz at 1 kHz and 1 MHz offsets, respectively. It consumes 6.709 μW at a 1 V supply and occupies an active CMOS area of 0.1095 mm2.