Convolutional Neural Networks (CNN) continue to dominate research in the area of hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its effectiveness in a variety of computer vision applications such as object segmentation, image classification, face detection, and traffic signs recognition, among others. However, there are numerous constraints for deploying CNNs on FPGA, including limited on-chip memory, CNN size, and configuration parameters. This paper introduces Ad-MobileNet, an advanced CNN model inspired by the baseline MobileNet model. The proposed model uses an Ad-depth engine, which is an improved version of the depth-wise separable convolution unit. Moreover, we propose an FPGA-based implementation model that supports the Mish, TanhExp, and ReLU activation functions. The experimental results using the CIFAR-10 dataset show that our Ad-MobileNet has a classification accuracy of 88.76% while requiring little computational hardware resources. Compared to state-of-the-art methods, our proposed method has a fairly high recognition rate while using fewer computational hardware resources. Indeed, the proposed model helps to reduce hardware resources by more than 41% compared to that of the baseline model.

This article proposes the design of a novel hardware embedded system used for automatic real-time road sign recognition. The algorithm used was implemented in two main steps. The first step, which detects the road signs, is performed by the maximally stable extremal region method on HSV color space. The second step enables the recognition of the detected signs by using the oriented fast and rotated brief features method. The novelty of the embedded hardware system, on an ARM processor, leads to a real-time implementation of the ADAS applications. The proposed system was tested on the Belgium Traffic Sign Detection and Recognition Benchmark and on the German Traffic Signs Datasets. The proposed approach attained a high detection and recognition rate with real-world situations. The achieved results are acceptable when compared to state-of-the-art systems. Request access from your librarian to read this article's full text.

Road sign recognition is part of the automatic driver assistance systems implemented on the dashboard of vehicles. The recognition task is often carried out based on a classification procedure manipulating the detected signs. Classification tasks can be resolved by the use of multilayer artificial neural network systems. This article proposes an optimized real-time on-chip hardware implementation of multilayer perceptron system used for road sign classification. Four architectural approaches were described: on the one hand, the classic and the serial optimized architectures that offer a very significant reduction in hardware resources, and, on the other hand, the parallel and the optimized architectures, which offer a much reduced, time execution. In order to benefit from the advantages of the allocated hardware resources and the classification of the runtime process, these four architectures have been implemented on field programmable gate array Virtex-6 devices and their performances were quantified and evaluated according to a cost criterion. The energy dissipated by each of these architectures was measured; the achieved results have allowed us to conclude that the serial optimized architecture is the optimal solution, since it creates a tradeoff between the low cost, and the energy efficiency, and still real-time for the considered application.

Quantization-aware training (QAT) has emerged as a key strategy for enabling efficient deep learning inference on resource-constrained platforms. Yet, most existing approaches rely on static, manually selected numeric formats—fixed-point or floating-point—and fixed bit-widths, limiting their adaptability and often requiring extensive design effort or architecture search. In this work, we introduce a novel QAT framework that breaks this rigidity by jointly learning, during training, both the numeric representation format and the associated bit-widths in an end-to-end differentiable manner. At the core of our method lies a unified parameterization that is capable of emulating both fixed- and floating-point arithmetic, paired with a bit-aware loss function that penalizes excessive precision in a hardware-aligned fashion. We demonstrate that our approach achieves state-of-the-art trade-offs between accuracy and compression on MNIST, CIFAR-10, and CIFAR-100, reducing average bit-widths to as low as 1.4 with minimal accuracy loss. Furthermore, FPGA implementation using Xilinx FINN confirms over $5\times$ LUT and $4\times$ BRAM savings. This is the first QAT method to unify numeric format learning with differentiable precision control, enabling highly deployable, precision-adaptive deep neural networks.