Drowsiness detection is crucial for ensuring the safety of individuals engaged in high-risk activities. Numerous studies have explored drowsiness detection techniques based on EEG signals, but these have typically been validated on computers, which limits their portability. In this paper, we introduce the design and implementation of a drowsiness detection technique utilizing EEG signals, executed on a Zynq7020 System on Chip (SoC) as part of a Pynq-Z2 module. This approach is more suitable for portable applications. We have implemented the Discrete Wavelet Transform (DWT) and feature extraction functions as intellectual property (IP) cores, while other functions run on the ARM processor of the Zynq7020.

Nonlinear optimization is a central component of visual odometry and simultaneous localization and mapping (SLAM), but its repeated small- and medium-scale linear algebra operations are difficult to deploy efficiently on embedded hardware. This paper presents a synthesizable C++ library for AMD/Xilinx Vitis high-level synthesis (HLS) that provides field-programmable gate array (FPGA)-oriented dense linear algebra kernels and Lie-group primitives on SO(3) and SE(3). The library supports configurable scalar types, including IEEE floating point, posit arithmetic, and reduced-precision floating-point formats, enabling design-space exploration between numerical accuracy and hardware cost. The proposed kernels are integrated into the back-end of a monocular direct mesh-based visual SLAM system and evaluated on an AMD/Xilinx Kria KV260 platform. Compared with the software reference running on the embedded processor, the integrated FPGA implementation reduces the end-to-end optimization iteration time from 32.0 ms to 8.9 ms, corresponding to a speed-up of 3.6×, and reduces the dominant kernel latency from 25.0 ms to 4.9 ms. The most resource-efficient reduced-precision configuration reduces lookup table (LUT) usage by 29.6%, flip-flop (FF) usage by 25.7%, block random-access memory (BRAM) usage by 25.9%, and digital signal processor (DSP) usage by 38.6% relative to the floating-point hardware baseline, while keeping the relative trajectory error within 1.42%. The results show that Lie-group-aware optimization back-ends can be mapped to embedded FPGAs efficiently when fixed-size algebraic kernels, synthesis-aware memory structures, and configurable arithmetic are considered together.

Quantization-aware training (QAT) has emerged as a key strategy for enabling efficient deep learning inference on resource-constrained platforms. Yet, most existing approaches rely on static, manually selected numeric formats—fixed-point or floating-point—and fixed bit-widths, limiting their adaptability and often requiring extensive design effort or architecture search. In this work, we introduce a novel QAT framework that breaks this rigidity by jointly learning, during training, both the numeric representation format and the associated bit-widths in an end-to-end differentiable manner. At the core of our method lies a unified parameterization that is capable of emulating both fixed- and floating-point arithmetic, paired with a bit-aware loss function that penalizes excessive precision in a hardware-aligned fashion. We demonstrate that our approach achieves state-of-the-art trade-offs between accuracy and compression on MNIST, CIFAR-10, and CIFAR-100, reducing average bit-widths to as low as 1.4 with minimal accuracy loss. Furthermore, FPGA implementation using Xilinx FINN confirms over $5\times$ LUT and $4\times$ BRAM savings. This is the first QAT method to unify numeric format learning with differentiable precision control, enabling highly deployable, precision-adaptive deep neural networks.

Differentiable rasterization enables image inversion by providing gradients of image-based losses with respect to camera and scene parameters, and has become a practical foundation for inverse graphics and photometric estimation on GPUs. However, the real-time deployment of differentiable rendering in embedded perception remains challenging due to the high cost of per-pixel sampling and gradient computation. In this work, we present an nvdiffrast-inspired differentiable rasterization engine implemented on FPGA and demonstrate its use in a simplified dense photometric pose-refinement task. Our design follows the modular philosophy of nvdiffrast while specializing it for deterministic, low-latency hardware execution. We implement point-sampled triangle rasterization with hard z-buffer visibility, perspective-correct interpolation, and an analytic antialiasing stage that yields stable, non-zero gradients at silhouettes and occlusion boundaries. Unlike GPU pipelines where texturing behavior may be hardware defined, our FPGA implementation controls the texture sampler, enabling a fused rasterize–interpolate–texture operator with a matched backward pass. Beyond pixelwise gradients, we introduce an on-device accumulation scheme that directly forms Gauss–Newton normal-equation terms, enabling second-order pose updates with substantially fewer iterations than gradient descent. We validate forward rendering and derivatives against a GLSL reference implementation, and report FPGA resource utilization and runtime. The core rasterization and analytic antialiasing pipeline achieves 2.5 ms per frame, while the full textured keyframe-projection operator runs in 8 ms per frame on an AMD Kria KV260. In a dense photometric pose-refinement evaluation on synthetic and real sequences, the proposed Jacobian accumulation reduces the number of optimization iterations required for convergence, improving time-to-solution despite the added cost of texturing. Together with a post-implementation on-chip power estimate of 3.662 W and an estimated 29.3 mJ per full-resolution differentiable rendering iteration, these results provide an implementation-level estimate of the accelerator’s power envelope for real-time photometric tracking and refinement.