In this paper, a generalized analysis and design methodology of a dual-band branch-line coupler (BLC) is presented. The proposed design, although based on the prevalent method of replacement of various arms of a single-band BLC with an equivalent T-/Pi-network, simplifies the design approach by only replacing either pair of arms and therefore provides four distinct topologies. Closed-form design equations along with insightful comments are reported for all the four topologies of the BLC. A number of cases are investigated to demonstrate the effectiveness of the proposed design for equal and unequal power division ratio and band-ratio (= f₂}/f₁ ). As an application, a novel dual-band crossover as a cascade of BLCs is also presented. While investigating the limitations of previous designs, a strategy to obtain the crossover with so far the widest band-ratio and simple layout is also presented. An unequal power division dual-band BLC and a dual-band crossover are designed which operate at 1/2 and 1/4 GHz, respectively. These designs are validated from the electromagnetic simulations and prototypes implemented on RT/Duroid 5880 substrate.

This paper reports design of a new dual-band T-type impedance transformer also exhibiting DC-blocking feature. The design aims at achieving matching for frequency-dependent complex loads having distinct values at two arbitrary frequencies to Z s (here, 50 Ω). A step-wise analysis on the developed dual-band impedance transformer provides simple closed-form design equations. The design is verified by simulation in Agilent ADS. For experimental verification a PCB prototype is fabricated using FR-4 material, operating at 1.45 GHz and 2.61 GHz. A good result is obtained confirming the theory and simulation.

This paper presents a dual-band impedance transformer for real source and load impedances that is capable of providing matching at two arbitrary frequencies. There are two possible configurations of the proposed technique, and both the configurations are simple and possess flexibility to cater to wide range of impedance environments. A very useful feature of the design is its inherent ability to provide DC isolation. A prototype, which works at 1 GHz and 2 GHz, fabricated using Roger's RO4350B laminate validates the proposed design with a good match between theoretical and experimental results. In addition, a dual-band T-junction power divider is reported to demonstrate the usefulness of the proposed impedance transformer.

In this paper, enhanced designs of port-extended branch-line coupler (BLC) are presented. Initially, the analysis of the conventional dual-band port-extended equal-division BLC is presented to deduce its operation from Riblet's viewpoint. Subsequently, it is shown that extending the Riblet's concept to dual-band design results in a novel dual-band BLC with arbitrary power division ratios. It has also been identified that the proposed design possesses a free design variable that allows realization of BLC with higher band-ratio. Furthermore, another BLC structure, capable of achieving enhanced band-ratio, utilizing two-section transmission line at each port is also proposed. All the reported design equations are in closed form and are very simple and do not go beyond a second-degree polynomial. The effectiveness of the proposed technique is demonstrated through test cases for equal and unequal power division ratio and for numerous band-ratio (=f ₂ /f ₁ ). The good agreement between the electromagnetic simulated results and the measured results from the two unequal power division BLC prototypes, on Rogers RO4003C substrate, operating at 1.2 GHz/2.52 GHz and 1 GHz/2 GHz validate the proposed approach.

A novel dual-band 3-dBWilkinson power divider (WPD) is presented that requires only partial port extension. The design methodology is based on the impedance matching technique and is very simple and intuitive with very simple closed-form formulations. The proposed technique has free variable(s) that add extra flexibility during the design and implementation. Continuous variation of isolation element(s) with band ratio ( $= f_{2}/f_{1}$ ) is no more required and is a distinct feature of this approach when compared with the conventional port extension technique. To enhance the band-ratio further, a technique, which utilizes port extension on all ports, is also demonstrated through an example. The band ratio of the proposed WPD is moderately wide, starting from 1.5 and going beyond 4. A flowchart of the proposed scheme is also reported that aids the systematic design procedure. The presented theory is validated through design and measurement of a prototype fabricated to operate at 0.9/3.5 GHz concurrently. The simulation and the measurement exhibit good agreement.

This paper presents a new design methodology for broadband Doherty architecture using the three-port input and output networks technique. The proposed topology was developed to overcome the Doherty power amplifier (DPA) bandwidth limitations. The output three-port network performs the impedance matching from any load impedance to the optimum loads for both main and peaking transistors and also combines the power delivered from the two devices at any power ratio. On the other hand, the input-splitting network is proposed for matching the input impedances of the two transistors to the source impedance. The freedom in choosing the power division ratio of the input network enables us to achieve a tradeoff between efficiency and linearity. Also, it provides a way to accomplish the phase compensation using an arbitrary phase difference between the two branches of the Doherty power amplifier and thus, helps obviate the need of the highly bandwidth limiting offset lines found in the Doherty design. A two-stage broadband Doherty power amplifier is implemented using 0.25-um GaN HEMT MMIC process to validate the proposed topology. The fabricated DPA was measured under both continuous wave (CW) and modulated signal at different operating frequencies. Across 3.3–3.7 GHz, the implemented DPA delivers a maximum output power exceeding 42 dBm, power added efficiency (PAE) over 52 % at the peak power and over 38 % in the back-off state over the operating 400 MHz bandwidth. The fully integrated circuit has a chip-size of 4.4 mm $\times\,\,3.5$ mm.