With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the “storage wall”, it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the “storage wall” problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed.

In high-integration electronic components, the insulated-gate bipolar transistor (IGBT) power module has a high working temperature, which requires reasonable thermal analysis and a cooling process to improve the reliability of the IGBT module. This paper presents an investigation into the heat dissipation of the integrated microchannel cooling plate in the silicon carbide IGBT power module and reports the impact of the BL series micropump on the efficiency of the cooling plate. The IGBT power module was first simplified as an equivalent-mass block with a mass of 62.64 g, a volume of 15.27 cm³, a density of 4.10 g/cm³, and a specific heat capacity of 512.53 J/(kg·K), through an equivalent method. Then, the thermal performance of the microchannel cooling plate with a main channel and a secondary channel was analyzed and the design of experiment (DOE) method was used to provide three factors and three levels of orthogonal simulation experiments. The three factors included microchannel width, number of secondary inlets, and inlet diameter. The results show that the microchannel cooling plate significantly reduces the temperature of IGBT chips and, as the microchannel width, number of secondary inlets, and inlet diameter increase, the junction temperature of chips gradually decreases. The optimal structure of the cooling plate is a microchannel width of 0.58 mm, 13 secondary inlets, and an inlet diameter of 3.8 mm, and the chip-junction temperature of this structure is decreased from 677 °C to 77.7 °C. In addition, the BL series micropump was connected to the inlet of the cooling plate and the thermal performance of the microchannel cooling plate with a micropump was analyzed. The micropump increases the frictional resistance of fluid flow, resulting in an increase in chip-junction temperature to 110 °C. This work demonstrates the impact of micropumps on the heat dissipation of cooling plates and provides a foundation for the design of cooling plates for IGBT power modules.

The rapid development of micro/nano systems promotes the progress of micro energy storage devices. As one of the most significant representatives of micro energy storage devices, micro hydrogen fuel cells were initially studied by many laboratories and companies. However, hydrogen storage problems have restricted its further commercialization. The γ-graphdiyne (γ-GDY) has broad application prospects in the fields of energy storage and gas adsorption due to its unique structure with rigid nano-network and numerous uniform pores. However, the existence of various defects in γ-GDY caused varying degrees of influence on gas adsorption performance. In this study, Lithium (Li) was added into the intrinsic γ-GDY and vacancy defect γ-GDY (γ-VGDY) to obtain the Li-GDY and Li-VGDY, respectively. The first-principles calculation method was applied and the hydrogen storage performances of them were analysed. The results indicated that the best adsorption point of intrinsic γ-GDY is H2 point, which located at the centre of a large triangular hole of an acetylene chain. With large capacity hydrogen storage, doping Li atom could improve the hydrogen adsorption property of intrinsic γ-GDY; meanwhile, vacancy defect inspires the hydrogen storage performance further of Li-VGDY. The mass hydrogen storage density for Li₂H₅₆-GDY and Li₂H₅₆-VGDY model were 13.02% and 14.66%, respectively. Moreover, the Li₂H₅₆-GDY and Li₂H₅₆-VGDY model had same volumetric storage density, with values that could achieve 5.22 × 10⁴ kg/m³.

With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used bonding method for these systems because of its excellent thermal, electric, and mechanical performance. However, relatively little work has been performed to analyze its height uniformity. In this study, the simulation and experimental methods were used to analyze the Au bump height uniformity. Firstly, the electroplating process of Au bump under different flow field parameters was simulated by COMSOL software. The simulated results indicated that the Au⁺ concentration polarization was the significant reason that caused the non-uniform distribution of Au bump along the wafer radius. Meanwhile, the flow field parameters, such as inlet diameter, inlet flow, titanium (Ti), wire mesh height, and Ti wire mesh density, were optimized, and their values were 20 mm, 20 L/min, 12 mm, and 50%, respectively. Subsequently, the Au bump height uniformity under different current densities was analyzed through an experimental method based on these flow field parameters. The experimental results showed that the increases of current density would decrease the Au bump height uniformity. When the current density was 0.2 A/dm², the average height, range, and deviance values of Au bump were 9.04 μm, 1.33 μm, and 0.43 μm, respectively, which could reach the requirement of high density and precision for 2.5D/3D integrated packaging.

Copper (Cu) interconnections have been widely used in advanced electronic packaging due to their outstanding thermal and electric properties. Preparing a smooth and uniform Cu seed thin layer is one of the critical processes to obtain high-reliability Cu interconnections. The barrier layer between Cu and silicon (Si) devices is necessary to prevent the inter-diffusion between Cu and Si. However, little work has been done on the surface roughness analysis of the Cu seed layer deposited on the diffusion barrier layer. In this paper, the influences of deposition thickness, incident energy, barrier layer temperature, and surface morphology on the surface roughness of the Cu seed layer deposited on α-titanium (α-Ti) barrier layer were studied in detail by the molecular dynamics (MD). The simulation results indicated that appropriate parameters have a beneficial effect on reducing the surface roughness, and the surface morphology of the Cu seed layer strongly connects with that of the barrier layer. These results provided a foundation for optimizing the quality of the Cu seed layer.