We propose the body floating and self-bias technique, in which the body of the transistor is connected to its drain through a resistance (13.6 kΩ in this work). A low-power 3-9-GHz CMOS low-noise amplifier (LNA) using the technique for sub-6-GHz 5G systems is reported. An enhancement in S ₂₁ and noise figure (NF) of the LNA is achieved due to the forward body-to-source bias ( V _BS ) (i.e., small threshold voltage V _th ) and the transistors being free from the substrate leakage. Low power is achieved since low supply voltage ( V _DD ) of 1 or 0.8 V is applicable because of small V _th . At V _DD of 1 V, the LNA consumes 3.3 mW and achieves prominent S ₁₁ of - 10.1 to -41.6 dB, S ₂₁ of 10.7 dB, and NF of 2.89 dB for 3-9 GHz. At V _DD of 0.8 V, the LNA consumes 1.36 mW and achieves S ₁₁ of - 10 to -45.8 dB, S ₂₁ of 9.4 dB, and NF of 3.46 dB. To the authors' knowledge, both are one of the lowest power values ever reported for CMOS LNAs with bandwidth greater than 6 GHz and NF under 3.5 dB.

We demonstrate a low-power ( $P_{D}$ ) and high-gain 21–29-GHz low-noise amplifier (LNA) in 90-nm CMOS for 28-GHz 5G systems. Current-reused architecture is adopted for low $P_{D}$ . Gain-boosting and body-floating techniques are used for gain and NF enhancement. The LNA consumes 13.7 mW and achieves prominent $S_{21}$ of 21.6 dB, 3-dB bandwidth of 8.1 GHz (21.2–29.3 GHz), minimum noise figure (NF $_{\mathrm {min}}$ ) of 2.74 dB, average NF (NF $_{\mathrm {ave}}$ ) of 2.99 dB for 21–29 GHz, and figure of merit (FOM) of 61.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of −9 dBm at 28 GHz. The chip size is only 0.348 mm ² . To the authors’ knowledge, the NF and FOM performance are one of the best results ever reported for millimeter-wave CMOS LNAs with bandwidth greater than 7 GHz and $P_{D}$ lower than 15 mW.

A low-power and low noise-figure (NF) 3.1–23.7-GHz CMOS variable-gain amplifier (VGA) is presented. The VGA composes of a complimentary common-source (CCS) first stage, followed by a common-source (CS) second stage. Low power and NF and wideband $S_{11}$ and $S_{21}$ are achieved due to the current-reused CCS input stage with multiple inductive impedance matching and gain compensation. A large gain tuning range (with low NF) is achieved due to the concurrent gate–voltage tuning (or current steering) of the first and the second stages. The VGA consumes 5.85 mW (at $V_{\mathrm{ctrl}}$ of 1 V) and achieves excellent 3-dB bandwidth ( $f_{3\,\mathrm{dB}})$ of 20.6 GHz (3.1–23.7 GHz), maximum $S_{21}$ of 11.9 dB, minimum NF (NF $_{\mathrm{min}})$ of 2.53 dB, average NF (NF $_{\mathrm{avg}})$ of 3.97 dB, small group delay (GD) variation of $\pm$ 16.5 ps, and input third-order intercept point (IIP3) of $-$ 6.5 dBm. Moreover, the VGA achieves a decent gain tuning range of 23.4 dB ( $-$ 5.4 to 18 dB) for $V_{\mathrm{ctrl}}$ of 0.6–1.6 V. The chip area is 0.364 mm $^{2}$ .

We report the design and analysis of a 28 GHz CMOS low-noise amplifier (LNA) and variable-gain amplifier (VGA1) using coupled-transmission-line (CTL)-feedback technique, and another VGA (VGA2) without CTL-feedback for contrast. The CTL in conjunction with a coupling capacitance ( $C_{\text{ctl}})$ contributes an in-phase gain at the output of the input stage. Over 21.9–29.1 GHz, 0.6–2.4 dB boosting in $S_{\text{21}}$ and 0.42–1.17 dB reduction in noise figure (NF) are achieved. The body-floating technique is used for NF reduction due to effective suppression of the substrate noise. An auxiliary-gain-linearity-enhancement (AGLE) stage is included in parallel with the output stage for gain and linearity boosting since it contributes an in-phase gain and exhibits better linearity due to higher drain–source voltage ( $V_{\text{DS}})$ . For VGA1 and VGA2, an analog current-steering switch transistor $M_{\text{5}}$ is in parallel with the output stage to tune its overdrive and $V_{\text{DS}}$ for fine tuning of $S_{\text{21}}$ . Digital switch transistor $M_{\text{6}}$ (in conjunction with the coupling capacitance $C_{\text{3}}$ and resonant inductance $L_{\text{res}})$ is in parallel with the gain stage to control its ac $V_{\text{DS}}$ for coarse tuning of $S_{\text{21}}$ . VGA1 adopts DTMOS-with- $R_{B}$ switch for lower on-state ( $R_{\text{ch,on}})$ and higher off-state channel resistance ( $R_{\text{ch,off}})$ . This leads to $S_{\text{21}}$ tuning range boosting. The LNA consumes 9.5 mW and achieves $S_{\text{21}}$ of 21.8 $\pm$ 1.5 dB for 21.9–29.1 GHz ( $f_{\text{3\,dB}}$ $=$ 7.2 GHz), minimum NF (NF $_{\text{min}})$ of 1.98 dB, and average NF (NF $_{\text{avg}})$ of 2.32 dB, and figure-of-merit (FOM $_{\text{2}})$ of 74.1 nm $\cdot $ GHz $^{\text{2/3}}$ /mW $^{\text{1/3}}$ . VGA1 consumes 13.2 mW and achieves $S_{\text{21}}$ of 20.1 $\pm$ 1.5 dB for 20.5–27.6 GHz ( $f_{\text{3\,dB}}$ $=$ 7.1 GHz), $S_{\text{21}}$ tuning range of 36.8 dB, NF $_{\text{min}}$ of 1.74 dB, NF $_{\text{avg}}$ of 2.1 dB, and FOM $_{\text{2}}$ of 66.5 nm $\cdot $ GHz $^{\text{2/3}}$ /mW $^{\text{1/3}}$ . The NF $_{\text{avg}}$ and FOM $_{\text{2}}$ are one of the best results ever reported for LNAs and VGAs with $f_{\text{3\,dB}}$ greater than 5 GHz and power dissipation lower than 15 mW.

We demonstrate a low-power $(P_{D})$ , low-noise, and high-gain 22.7–29.7-GHz variable-gain amplifier (VGA) in 90-nm CMOS for 28-GHz 5G systems. Low $P_{D}$ and wide gain tuning range are achieved due to the use of the self-body-to-drain bias through body-floating resistance and the current-reused topology with auxiliary current steering. Input noise matching and body-floating techniques are used for noise figure (NF) enhancement. VGA consumes 7.4 mW and achieves $S_{21}$ tuning range of 23.7 dB (19.2 to −4.5 dB) at 26 GHz. At $V_{\mathrm {ctrl}}$ of 0 V (i.e., maximum gain), VGA attains $S_{21}$ of 16.2–19.2 dB for 22.7–29.7 GHz [i.e., 3-dB bandwidth ( $f_{3\,\mathrm {dB}}$ ) equal to 7 GHz], minimum noise figure (NF $_{\mathrm {min}}$ ) of 2.39 dB at 26.5 GHz, average NF (NF $_{\mathrm {avg}}$ ) of 2.76 dB for 22.5–29.5 GHz, small group delay (GD) variation of ± 14.7 ps for 18–30 GHz (i.e., decent phase linearity), and input third-order intercept point (IIP3) of −12.7 dBm at 28 GHz. The chip area is 0.383 mm ² .

In this paper, we demonstrate a low-loss and high-linearity DC-38 GHz CMOS SPDT switch for 5G multi-band communications in 0.18 μm CMOS. Traveling-wave matching (CLCL network) is used for the output-port (ports 2 and 3) matching and isolation enhancement, while π-matching (CLC matching) is adopted for the input-port (port 1) matching. Positive/negative gate-bias is adopted for linearity enhancement because larger P_in (i.e., AC signal with larger negative V_in) is required to conduct the off-state series switch transistor. Negative-body bias is used for insertion-loss reduction because the off-state series switch transistor is closer to an open state. The SPDT switch achieves insertion loss of 0.4–1.4 dB, 3.6–4.3 dB, and 4.5–5.9 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. Moreover, the SPDT switch achieves isolation of 37.5–59.4 dB, 25.7–28.7 dB, and 24.3–25.2 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. At 28 GHz, the SPDT switch achieves remarkable input 1-dB compression point (IP_1dB) of 25.6 dBm, close to the simulated one (28 dBm). To the authors’ knowledge, this is one of the best IP_1dB results ever reported for millimeter-wave (mm-wave) SPDT switches.