We propose the body floating and self-bias technique, in which the body of the transistor is connected to its drain through a resistance (13.6 kΩ in this work). A low-power 3-9-GHz CMOS low-noise amplifier (LNA) using the technique for sub-6-GHz 5G systems is reported. An enhancement in S ₂₁ and noise figure (NF) of the LNA is achieved due to the forward body-to-source bias ( V _BS ) (i.e., small threshold voltage V _th ) and the transistors being free from the substrate leakage. Low power is achieved since low supply voltage ( V _DD ) of 1 or 0.8 V is applicable because of small V _th . At V _DD of 1 V, the LNA consumes 3.3 mW and achieves prominent S ₁₁ of - 10.1 to -41.6 dB, S ₂₁ of 10.7 dB, and NF of 2.89 dB for 3-9 GHz. At V _DD of 0.8 V, the LNA consumes 1.36 mW and achieves S ₁₁ of - 10 to -45.8 dB, S ₂₁ of 9.4 dB, and NF of 3.46 dB. To the authors' knowledge, both are one of the lowest power values ever reported for CMOS LNAs with bandwidth greater than 6 GHz and NF under 3.5 dB.

This paper reports two four-way 94-GHz power amplifiers (PAs) for radar sensors in 90-nm CMOS technology. The first PA (PA1) comprises a two-stage common-source (CS) cascaded input stage with wideband π -match input, interstage and output networks, followed by a two-way CS gain stage using Y-shaped divider and combiner, and a four-way CS output stage using dual Y-shaped divider and combiner. At each branch's input terminal (i.e., drain terminal of the parallel CS output stage), the low-loss dual Y-shaped combiners can convert the serial RL load into the impedance for optimal output power (Pout) and power-added efficiency (PAE). To enhance power gain and PAE performance, the second PA (PA2) adopts a two-stage positive-feedback CS cascaded input stage using λ/2 transmission line. The circuit architecture of the gain and output stages is the same as that of PA1. PA1 achieves power gain of 16, 21, and 12 dB, respectively, at 60, 77, and 94 GHz. In addition, PA1 achieves P _out of 13.2, 12, and 10.6 dBm, respectively, at 60, 77, and 94 GHz. The corresponding peak PAE is 20%, 16%, and 10.2%, respectively, at 60, 77, and 94 GHz. At 94 GHz, PA2 achieves power gain of 20 dB, Pout of 16.8 dBm, and peak PAE of 16.4%. The overall performance of the two CMOS PAs is remarkable in V -band and W -band.

A low-power W-band gain-enhanced CMOS down-conversion mixer for millimeter-wave-to-baseband pulsed-radar receiver is presented. To enhance the equivalent load impedance while keeping the transconductance (gm) of the RF gm stage unchanged and achieving prominent IF bandwidth, we propose a novel core IF load, which is based on the parallel combination of the cross-coupled PMOS transistors (CCPT) and the series RL circuit (i.e., CCPT-RL-based core IF load). The down-conversion mixer comprises a double-balanced Gilbert-cell-based mixer core with an inductive-peaking current-bleeding RF gm stage and a CCPT-RL-based core IF load, two elliptic baluns, and a source follower buffer. Compared with the traditional down-conversion mixer for direct conversion receiver, conversion gain (CG), and noise figure (NF) can be significantly enhanced. For 88~ 100 GHz, the mixer consumes 5 mW and achieves excellent RF-port input reflection coefficient (S₁₁) of -9.6~-19.1 dB and LO-port input reflection coefficient (S₂₂) of -5.5~-21.9 dB. In addition, the mixer achieves excellent CG of 11.8~ 14.6 dB, NF of 14.2~ 15.2 dB, and LO-RF isolation of 34.6~ 35.3 dB-one of the best CG, NF, and LO-RF isolation results ever reported for a W-band down-conversion mixer.

We demonstrate a low-power ( $P_{D}$ ) and high-gain 21–29-GHz low-noise amplifier (LNA) in 90-nm CMOS for 28-GHz 5G systems. Current-reused architecture is adopted for low $P_{D}$ . Gain-boosting and body-floating techniques are used for gain and NF enhancement. The LNA consumes 13.7 mW and achieves prominent $S_{21}$ of 21.6 dB, 3-dB bandwidth of 8.1 GHz (21.2–29.3 GHz), minimum noise figure (NF $_{\mathrm {min}}$ ) of 2.74 dB, average NF (NF $_{\mathrm {ave}}$ ) of 2.99 dB for 21–29 GHz, and figure of merit (FOM) of 61.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of −9 dBm at 28 GHz. The chip size is only 0.348 mm ² . To the authors’ knowledge, the NF and FOM performance are one of the best results ever reported for millimeter-wave CMOS LNAs with bandwidth greater than 7 GHz and $P_{D}$ lower than 15 mW.

We present the design and analysis of coupled-line-based Ka-band CMOS power dividers. A single spiral structure with a symmetrical layout is adopted to achieve a miniature area and small amplitude imbalance (AI) and phase difference (PD) performance. The first divider (divider-1) achieves S₂₁ and S₃₁ of -4.029 and -4.008 dB, respectively, at 33 GHz. The corresponding AI and PD are -0.021 dB and 0.369°, respectively. Moreover, the second divider (divider-2) achieves S₂₁ and S₃₁ of -4.093 and -4.055 dB, respectively, at 33 GHz. The corresponding AI and PD are -0.038 dB and 0.148°, respectively. The chip area is 1.7 x 10⁻⁴ λ₀², one of the smallest normalized chip area ever reported for millimeter-wave (mm-wave) dividers. The prominent results of the dividers indicate that they are suitable for power division/combination in mm-wave transceivers.

A spiral-coupled-line-based Ka-band (26.5-40 GHz) CMOS Wilkinson power divider with a shunt capacitor (C) at the input and a shunt RC (or C) between the outputs is reported. The spiral coupled line, i.e., two noninverting spiral transmission lines (TLs) with magnetic coupling, has a positive mutual inductance. This leads to a significant TL-length reduction (from about λ/7 to λ/12) for a specific TL series inductance. At 33 GHz, the power divider achieves prominent S ₁₁ of -21.5, S ₂₂ of -22.1, S ₃₃ of -22.1, S ₃₂ of -26.1, S ₂₁ of -4.063, and S ₃₁ of -4.052 dB. The corresponding amplitude imbalance (AI) and phase difference (PD) are -0.011 dB and -0.336°, respectively. Moreover, S11 is smaller than -10 dB for 0-45.3 GHz, corresponding to 137.3% fractional bandwidth (FBW). S32 is smaller than -10 dB for 24.1-40.2 GHz, covering the Ka-band and corresponding to 48.8% FBW. The power divider occupies a normalized area of 1.2 × 10 ^-4 λ ₀ ² , one of the smallest normalized chip areas ever reported for millimeter-wave power dividers.