Paulo César Comassetto de Aguirre

Prof. Dr. Paulo César Comassetto de Aguirre

Campus Alegrete, Universidade Federal do Pampa, Bagé, Rio Grande do Sul, Brazil
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Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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26 June 2023 in Eng
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MRMarcelo Romanssini
Marcelo Romanssini
Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
LSLucas C. Severo
Lucas C. Severo
AGAlessandro Girardi
Alessandro Girardi
Machine failure in modern industry leads to lost production and reduced competitiveness. Maintenance costs represent between 15% and 60% of the manufacturing cost of the final product, and in heavy industry, these costs can be as high as 50% of the total production cost. Predictive maintenance is an efficient technique to avoid unexpected maintenance stops during production in industry. Vibration measurement is the main non-invasive method for locating and predicting faults in rotating machine components. This paper reviews the techniques and tools used to collect and analyze vibration data, as well as the methods used to interpret and diagnose faults in rotating machinery. The main steps of this technique are discussed, including data acquisition, data transmission, signal processing, and fault detection. Predictive maintenance through vibration analysis is a key strategy for cost reduction and a mandatory application in modern industry.

5 September 2019 in IEEE Transactions on Circuits and Systems II: Express Briefs
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Journal Article
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Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
EBEdoardo Bonizzoni
Edoardo Bonizzoni
FMFranco Maloberti
Franco Maloberti
ASAltamiro Amadeu Susin
Altamiro Amadeu Susin
This brief presents a low-voltage inverter-based continuous-time sigma-delta modulator (CT-SDM). The inverter-based amplifiers are single-stage and their operating point is provided by a bulk-based current mirror. To improve the power-efficiency, a passive RC path is used to assist the amplifier of the first integrator. The proposed modulator was fabricated in a 180-nm CMOS process with an active area of 0.36 mm2. The modulator loop filter operates with a supply voltage of 0.45 V while the digital circuitry operates at 0.6 V. The modulator total power consumption is 28.72 μ W. For a 50-kHz signal bandwidth, the measured peak SNR/SNDR is 71.24/70.64 dB and the achieved DR is 78.3 dB, leading to a Schreier figure-of-merit of 170.70 dB.

4 July 2018 in IEEE Transactions on Circuits and Systems II: Express Briefs
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Journal Article
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Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
ASAltamiro Amadeu Susin
Altamiro Amadeu Susin
This brief presents a 0.6 V third-order continuous-time sigma-delta modulator (CT-SDM) based on single-stage inverter-based amplifiers. The designed amplifier uses an onchip bulk-bias technique to control the common mode output voltage and to mitigate process, voltage and temperature variations. Also, a negative resistance is used at the output of the amplifier to enhance dc gain. To increase power efficiency, a single-amplifier resonator is used in the loop filter. To enable this implementation a compensation technique to mitigate the effects of amplifier's finite dc gain in the resonator transfer function is presented. The proposed CT-SDM was fabricated in a 130-nm CMOS process with an active area of 0.232 mm 2 . The modulator achieves a 74.2 dB DR and peak SNDR/SNR of 59.43/69.04 dB for a 100 kHz signal bandwidth while consuming 89.50 μW from a 0.6-V power supply.

1 November 2018 in Electronics Letters
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Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
ASA.A. Susin
A.A. Susin
An inverter‐based operational transconductance amplifier (OTA) robust to process, voltage and temperature (PVT) variations is proposed in this Letter to enable the design of low‐voltage power‐efficient continuous‐time sigma‐delta modulators (CT‐SDMs). The proposed OTA significantly reduces the unity gain‐bandwidth variation across PVT corners while presenting a DC gain of 41.9 dB at nominal conditions when operated at 0.6 V. The effectiveness of the proposed circuit was verified in a 180 nm CMOS process by transistor‐level simulations including PVT variations and mismatch. Also, a 0.6 V third‐order CT‐SDM is designed to verify the robustness against voltage and temperature variations.

31 December 2022 in Journal of Integrated Circuits and Systems
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AGAlessandro Girardi
Alessandro Girardi
TDTailize De-Oliveira
Tailize De-Oliveira
SGSidinei Ghissoni
Sidinei Ghissoni
Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
LSLucas C. Severo
Lucas C. Severo
Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

22 June 2023 in Energies
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Luis Felipe Machado DutraLuis Felipe Machado Dutra
Luis Felipe Machado Dutra
AGAlessandro Girardi
Alessandro Girardi
Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
LSLucas C. Severo
Lucas C. Severo
Energy harvesting is a technology that can be applied to IoT systems to eliminate the need for batteries. Many types of energy sources are available for energy harvesting, such as light, thermal, vibration, and electromagnetic energy. Indoors, where most IoT devices are located, artificial light, such as from LED lamps, can be used for energy harvesting in circuits with very ultra-low power consumption. Integrated switch-capacitor DC-DC converters are required for this type of system to convert the harvested energy into a constant output voltage suitable for powering an electronic circuit. The idea of this work is to use a hysteretic feedback control consisting of comparators and a logic system to adjust the switching frequency and the voltage conversion ratio (VCR) of the converter. With this, the equivalent output resistance is tuned to a value that results in a constant output voltage. A new method for modeling the equivalent output resistance based on charge flow analysis is proposed, which also considers the effects of source resistance. An integrated energy-harvesting system consisting of a switched-capacitor DC-DC converter is implemented to obtain an output voltage of 400 mV using a small photovoltaic cell for energy harvesting from indoor light. The proposed system can power an ultra-low-power device between 20 μW and 40 μW with a minimum input voltage of 230 mV. Electrical simulation results show that the implemented converter can achieve a peak efficiency of 81.24% at an input voltage of 260 mV for a 20 μW load.