Lucas C. Severo

Lucas C. Severo


Research Focus & Metrics

Academic Career Length

14Years (2013-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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26 June 2023 in Eng
Verified
Journal Article
Open access
PDF file
MRMarcelo Romanssini
Marcelo Romanssini
Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
LSLucas C. Severo
Lucas C. Severo
AGAlessandro Girardi
Alessandro Girardi
Machine failure in modern industry leads to lost production and reduced competitiveness. Maintenance costs represent between 15% and 60% of the manufacturing cost of the final product, and in heavy industry, these costs can be as high as 50% of the total production cost. Predictive maintenance is an efficient technique to avoid unexpected maintenance stops during production in industry. Vibration measurement is the main non-invasive method for locating and predicting faults in rotating machine components. This paper reviews the techniques and tools used to collect and analyze vibration data, as well as the methods used to interpret and diagnose faults in rotating machinery. The main steps of this technique are discussed, including data acquisition, data transmission, signal processing, and fault detection. Predictive maintenance through vibration analysis is a key strategy for cost reduction and a mandatory application in modern industry.

1 April 2017 in Journal of Instrumentation
Verified
Journal Article
Closed access
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JAJ. Adolfsson
J. Adolfsson
APA. Ayala Pabon
A. Ayala Pabon
MBMarco Bregant
Marco Bregant
CBC. Britton
C. Britton
GBG. Brulin
G. Brulin
SZS. Zaporozhets
S. Zaporozhets

1 April 2019 in IEEE Transactions on Circuits and Systems I: Regular Papers
Verified
Journal Article
Closed access
LSLucas C. Severo
Lucas C. Severo
WNWilhelmus Van Noije
Wilhelmus Van Noije
This paper presents a 0.4-V ultra-low power (ULP) third-order active-RC complex band-pass filter (CxBPF) for Bluetooth low energy receivers prototyped in a 180 nm CMOS process. The ULP is reached by using single-stage inverter-based operational transconductance amplifiers (OTA) instead of two or more stages OTA. The effects of the low voltage gain and resistive loading are reduced by using a process and temperature robust negative transconductor connected to the virtual ground. The ultra-low voltage operation is reached by using only two stacked transistors and PMOS bulk forward bias. The CxBPF operates well down to 0.4V power supply and the experimental results present power dissipation of only 10.9 μW/pole, 1 MHz bandwidth centered at 2 MHz, image rejection rate of 34 dB, and 12.7 fJ FoM.

1 May 2017
Verified
Conference Paper
Closed access
HHHugo Hernandez
Hugo Hernandez
DCDionisio Carvalho
Dionisio Carvalho
BSBruno Sanches
Bruno Sanches
LSLucas C. Severo
Lucas C. Severo
WNWilhelmus Van Noije
Wilhelmus Van Noije
This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes a feedback control which reduces the common-mode voltage variations in terms of the Vds voltage of the bias transistor, and an enable/disable operation mode, which minimizes the power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to design the receiver circuit being robust to transient common-mode variations with low power consumption and high speed. The experimental DC power consumption of the transceiver is 4.6 mW at 1.25V power supply, where 1.1 mW is consumed by the receiver and 3.5 mW by the transmitter. The eye diagram proves the proper dynamic operation of the circuit until a data rate of 1.2Gbps.

31 December 2022 in Journal of Integrated Circuits and Systems
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Journal Article
Open access
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AGAlessandro Girardi
Alessandro Girardi
TDTailize De-Oliveira
Tailize De-Oliveira
SGSidinei Ghissoni
Sidinei Ghissoni
Paulo César Comassetto de AguirrePaulo César Comassetto de Aguirre
Paulo César Comassetto de Aguirre
LSLucas C. Severo
Lucas C. Severo
Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

1 March 2018 in Electronics Letters
Verified
Journal Article
Open access
PDF file
LSLucas C. Severo
Lucas C. Severo
WNW. Van Noije
W. Van Noije
An ultra‐low voltage and ultra‐low power programmable gain amplifier (PGA) using a closed‐loop single‐stage operational transconductance amplifier (OTA) and an input negative transconductor is proposed. The circuits are implemented in a 180 nm CMOS process using two stacked transistors and PMOS bulk forward bias to operate well down to 0.36 V, to be robust to PVT variations and to reach the bandwidth of low energy RF receivers. The PGA measured results at 0.36 V show a programmable voltage gain from 0.2 to 18.4 dB, 15.4 μW power dissipation, 0.98 MHz bandwidth and 0.0243 mm 2 area.