A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders.

Bandgap reference (BGR) circuits play a crucial role as voltage reference generators for other components within a variety of analog integrated circuits. Therefore, their power supply rejection ratio (PSRR), which represents the BGR’s ability to maintain a stable output in the presence of supply ripples, has a substantial impact on the overall circuit performance and is consequently worthy of attention. In this work, the design of a 65nm-CMOS BGR circuit and the computational approach to optimize its PSRR value are presented. Our proposed BGR circuit incorporates a modification in the op-amp structure to enhance the PSRR parameter. Detailed explanations of the proposed op-amp’s differential gain calculation and the PSRR parameter formula are provided. Additionally, we employ the particle swarm optimization (PSO) algorithm to maximize PSRR while satisfying other specifications. Four distinct approaches for utilizing the inertia weight parameter of the PSO algorithm are explored: two newly developed techniques (PSO – local exploitation orienter (PSO-LEO) and PSO – global exploration orienter (PSO-GEO)) together with two conventional approaches. A comprehensive comparative analysis reveals the superiority of our proposed PSO-GEO technique. Ultimately, our 65 nm CMOS bandgap circuit exhibits exceptional performance, featuring a temperature coefficient of 6.4056 ppm/°C and a PSRR of 99.9896 dB at 1 kHz. In conclusion, this work contributes substantially through op-amp architecture modification, PSRR optimization via the PSO algorithm, and introducing new inertia weight parameter utilization strategies and analyzing them.

Hardware architecture optimized for implementing the elliptic-curve Diffie–Hellman ephemeral (ECDHE) on 256-bit Montgomery elliptic curves presents unique challenges, particularly for resource-constrained IoT and mobile devices. This work aims to provide an efficient hardware implementation of ECDHE on Curve25519, including a dedicated finite state machine (FSM) designed to handle point multiplication and ECDHE operations, utilizing constant-time algorithms and a unified memory block for resource management. Additionally, we introduce an optimized modular computation unit that covers modular addition, subtraction, multiplication, and inversion. Our proposed hardware architecture enhances the efficiency of ECDHE operations while maintaining low resource utilization, considerably reduced latency, and low power consumption. Synthesized on the Xilinx Artix-7 platform, our design boasts 64,000 Slices and a clock speed of 102 MHz, and it computes an ECDHE scalar multiplication operation in 1.1 ms, consuming 117 mW. The proposed hardware design can be applied to various platforms, including mobile devices and IoT systems.