This paper introduces FPGA-based optimized implementation of Montgomery Modular Multiplier (MMM) architecture. The novel architecture of the proposed design enhanced the maximum frequency of the design and also the occupied area on the targeted FPGA. A Xilinx Virtex-6 FPGA implementation of the proposed architecture comparing with other related designs revealed that, our design occupies the smallest area, and the efficiency is enhanced in the range between 1.2 to 11.7 times the efficiency of other relevant designs. The proposed design is implemented as a modular multiplier for lightweight elliptic curve cryptography (ECC) over general GF(p). The proposed architecture is targeted the hardware implementation of lightweight cryptographic modules used on the System on Chip (SoC) and Internet of Things (IoT) devices.

This paper presents the FPGA-based implementation of compact montgomery modular multiplier (MMM). MMM serves as a building block commonly required in security protocols relying on public key encryption. The proposed design is intended for hardware applications of lightweight cryptographic modules that is utilized for the system on chip (SoC) and internet of things (IoT) devices. The proposed design is a modification in the structure of MMM without any multiplication or subtraction processes. The main target of the new modification is enhancing the performance and reducing the area of the MMM hardware module. The operands and internal variables of the proposed hardware circuit is optimized to be bounded to the smallest efficient size to minimize the area and the critical path delay. The proposed design was coded in VHDL, implemented in the Virtex-6 FPGA, and its performance was analyzed utilizing XILINX ISE tools. Our design occupies the smallest area comparing with other implementations on the same FPGA type. The proposed design saves in a range between 60.0 and 99.0% of the resources compared with other relevant designs.

Recently, studying of Maximum Distance Separable (MDS) matrix has become a topic of interest. The MDS matrix is the most important component of the diffusion layer in block ciphers. This paper introduces an optimized, low-cost hardware construction of Galois Field GF(2^8 ) 4×4 MDS matrix. The proposed design is implemented on Field programmable Gate Array (FPGA). The proposed design is synthesized targeting Virtex-7 FPGA using Xilinx ISE Design suite. Xilinx primitives LUT6 and LUT6_2 were used to control exactly the component placement in the design to maintain the minimum occupation area. The pipeline and parallel implementation techniques were used to improve the speed performance. The verification of the functionality of the proposed design has been proved using the ModelSim simulation tool. The synthesis result of the proposed design shows that, the new proposed architecture provides very competitive area and throughput trade-offs. In comparison with other related designs, the proposed design occupies the least area with the minimum time delay. The area of the developed MDS matrix design was significantly reduced, 68 LUT, with high throughput of 21.178 Gbps. The proposed design is a suitable candidate for lightweight cryptographic implementations.