This study focuses on the automatic generation control (AGC) system, which is crucial for maintaining balance between power generation and demand in power systems. The implementation of the AGC system needs to be more precise due to the increasing uncertainty surrounding renewable energy sources (RESs) and changes in demand. The objective of this study is to investigate the AGC functions in a two-area hybrid power system that combines a PV system with a reheat thermal system. To improve system performance, we utilize a proportional-integral (PI) controller. We utilized a recently developed optimization method, RIME, for tuning controller parameters. This technique has not been studied before in AGC processes. Furthermore, the optimization procedure utilizes a modified version of the integral time-multiplied absolute error (ITAE) objective function. The study compares the performance of the RIME-tuned PI controller under various scenarios, including changes in thermal system load, load variations in both areas, and robustness considerations, with well-known techniques in the literature, such as black widow optimization algorithm (BWOA), salp swarm algorithm (SSA), shuffled frog leaping algorithm (SFLA), firefly algorithm (FA) and genetic algorithm (GA). Our comparative study demonstrates that the proposed controller outperforms state-of-the-art approaches in terms of overshoot values and damping durations for both system frequency and tie-line power changes. The study provides valuable information on the effectiveness of the RIME-tuned PI controller in controlling AGC processes in complex hybrid power systems.

This paper introduces FPGA-based optimized implementation of Montgomery Modular Multiplier (MMM) architecture. The novel architecture of the proposed design enhanced the maximum frequency of the design and also the occupied area on the targeted FPGA. A Xilinx Virtex-6 FPGA implementation of the proposed architecture comparing with other related designs revealed that, our design occupies the smallest area, and the efficiency is enhanced in the range between 1.2 to 11.7 times the efficiency of other relevant designs. The proposed design is implemented as a modular multiplier for lightweight elliptic curve cryptography (ECC) over general GF(p). The proposed architecture is targeted the hardware implementation of lightweight cryptographic modules used on the System on Chip (SoC) and Internet of Things (IoT) devices.

A new time-based architecture for serial communication links is presented in this paper. The design is based on a low-power pulse-position modulator (PPM) as a transmitter and a low-power, single-cycle-latency time-to-digital converter (TDC) as a receiver. Using the proposed architecture, a 4 Gbps link over a 40 inch FR4 channel has been designed using a 1 GHz input clock signal and performance is compared with a serializer/deserializer (SerDes) link with the same data rate. The proposed architecture concentrates the transmitted signal energy in a significantly lower bandwidth than the conventional SerDes system at the same data rate. This allows simpler circuitry at the receiver side to recover the transmitted data, using smaller chip area and lower power dissipation. The technique can be readily expanded to modulate both edges of the signal, and the clock can also be embedded to avoid the need for a separate clock line.

The COVID-19 pandemic has affected people from almost every walk of life in general and academia in particular. It had a huge impact on teaching and learning resulting in a sudden shift from classroom and face-to-face teaching to distance and online teaching and learning. This sudden shift created a lot of ruckuses in the teaching of engineering disciplines. This study is pertinent to the examination of faculty perceptions of online teaching in Pakistani universities and the obstacles they face in teaching engineering students through the online mode during this pandemic. The research takes a quantitative and sample survey approach. A Google form questionnaire was used to collect the data from a sample of 91 faculty members from the engineering discipline of different universities in Pakistan during 2022. According to the study’s findings, faculty generally have a favorable opinion of virtual teaching in the context of COVID-19 for closing the achievement gap and guiding students’ futures in difficult times. However, they ran into a number of challenges when teaching online, including technological difficulties, problems with student participation, challenges with online tests and assessments, etc. The results of this study will urge educational institutions and policymakers to use the most up-to-date instructional methodologies and offer teachers ongoing professional development in order to improve the quality of online teaching, learning, and assessment in universities. Previous studies discussed a number of obstacles faced by students in virtual teaching in higher education, overlooking the perception and challenges faced by the engineering faculty. The present study replenishes this gap.

The present paper aims to propose a novel hybrid algorithm, where the Arithmetic Optimization Algorithm (AOA) and Rat Swarm Optimization (RSO) are employed for the proportional-integral-derivative (PID) controller to control the position of a micro-robotics system. In the algorithm proposed, we combine the exploratory mechanisms of AOA with RSO's exploitative behaviors. The proposed algorithm is employed for identifying the PID controller optimal parameters considering six different objective functions. Using CEC 2017 benchmark functions, the proposed hybrid is evaluated, and these functions’ performance is compared with the existing multiple algorithms. The statistical results are compared with the AOA, Jellyfish Search Optimization, and Harries Hawk Optimization algorithm for identifying the optimal PID controller settings considering multiple fitness functions. We consider performance indicators like PID controller parameters, rise time, settling time, and fitness values. The fetched simulation results revealed that, among all investigated fitness functions, the developed controller based on HAOARSO is the most effective algorithm for delivering global optimal solutions with less settling time and rise time, enabling the implementation on such optimization issues. Finally, the validation via MATLAB/Simulink simulations underscores the efficacy of the proposed algorithm.

A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The proposed link is shown to concentrate the signal energy in a low bandwidth while reducing clock jitter effect. A simulated 3 Gb/s 90 nm CMOS DTS link using a 500 MHz clock signal is also described to provide a flavor for a monolithic realization. As a proof of concept, 700 Mb/s and 1.6 Gb/s DTS-based links have been designed using a commercial FPGA board. The measured eye diagrams for the transmitted and received signals over a 40-inch FR4 channel are presented.