Deploying deep-learning detectors for printed circuit board (PCB) inspection on embedded hardware requires balancing detection performance against computational and memory constraints. This study evaluates a You Only Look Once version 8 medium (YOLOv8m) detector deployed on the AMD Kria KV260 (Advanced Micro Devices, Inc., Santa Clara, CA, USA) field-programmable gate array (FPGA) platform using the Vitis AI toolchain and a single DPUCZDX8G B4096 deep-learning processing unit (DPU) core at 275 MHz. The experimental subset comprised 1194 DeepPCB images covering all 11 board groups and six defect classes, including 959 training/internal-validation and 235 test images. The 32-bit floating-point (FP32) model achieved 93.5% mean average precision at an intersection-over-union threshold of 0.5 (mAP@50). Following 8-bit integer (INT8) post-training quantization, the model achieved 93.2% mAP@50 during on-board execution on the same images, while reducing nominal weight storage approximately fourfold. The measured end-to-end throughput was 0.87 frames per second (FPS). Stage-level profiling yielded 333.2 ms preprocessing, 206.8 ms DPU inference, and 609.0 ms postprocessing per frame, indicating that host-side processing, particularly postprocessing, dominated end-to-end latency. An exploratory throughput-only comparison on the same platform yielded 3.92 FPS for YOLOX-Nano and 1.72 FPS for YOLOX-Tiny. These results establish a documented deployment baseline for a medium-scale YOLO detector on a low-cost FPGA platform and highlight the importance of host-side processing in determining end-to-end inference throughput.