This letter demonstrates vertical GaN junction barrier Schottky (JBS) rectifiers fabricated with novel ion implantation techniques. We used two different methods to form the lateral p-n grids below the Schottky contact: 1) Mg implantation into n-GaN to form p-wells and 2) Si implantation into p-GaN to form n-wells. Specific differential ON-resistances ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of 1.5–2.5 $\text{m}\Omega ~\cdot $ cm ² and 7–9 $\text{m}\Omega ~\cdot $ cm ² were obtained in the Mg-implanted and Si-implanted JBS rectifiers, respectively. A breakdown voltage of 500–600 V was achieved in both devices, with a leakage current at high reverse biases at least 100-fold lower than conventional vertical GaN Schottky barrier diodes. The impact of n-well and p-well widths on the ${R}_{ \mathrm{\scriptscriptstyle ON}}$ and BV was investigated. Fast switching capability was also demonstrated. This letter shows the feasibility of forming patterned p-n junctions by novel ion implantation techniques, to enable high-performance vertical GaN power devices.

Record DC power has been demonstrated in AlGaN/GaN high electron mobility transistors fabricated using a substrate replacement process in which a thick diamond substrate is grown by chemical vapor deposition following removal of the original Si substrate. Crucial to the process is a ~30 nm thick SiN interlayer that has been optimized for thermal resistance. The reductions obtained in self-heating have been quantified by transient thermoreflectance imaging and interpreted using 3D numerical simulation. With a DC power dissipation level of 56 W/mm, the measured average and maximum temperatures in the gate-drain access region were 176 °C, and 205 °C, respectively.

A long‐standing goal of GaN device research has been the development of a reliable, well‐controlled process for p‐GaN formation by ion implantation. Results to date have indicated an activation of 1% or less using high‐temperature rapid thermal annealing (RTA) techniques and coimplantation. Although Mg is a relatively deep acceptor, this is still much less than the theoretically achievable value (8.2% based on the 160 meV acceptor level). A multicycle RTA process is presented that is capable of achieving up to 8% activation of the Mg‐implanted GaN. This approaches the theoretical value, and represents a significant step in GaN device research.

Gallium nitride (GaN) high electron-mobility transistors (HEMTs) offer considerable high-power operation but suffer in reliability due to potentially damaging self-heating. In this study, self-heating in AlGaN/GaN HEMTs on high conductivity substrates is assessed using a high-resolution thermoreflectance (TR) imaging technique, to compare the thermal response between GaN-on-Si, GaN-on-Diamond, and GaN-on-4H-SiC. The TR method accuracy at high-power density is verified using a nonlinear coefficient of TR (CTR) as a function of temperature. The acquired steady-state thermal maps give a thermal resistance of 11.5 mm · K/W for GaN-on-Si (based on peak channel temperature), compared to 2.7 and 3.3 mm · K/W for GaN-on-SiC and GaN-on-diamond substrates, respectively. The tested GaN-on-diamond HEMT exhibits similar heating rates to those seen on a SiC substrate, with a slightly higher peak temperature, which indicates a higher thermal boundary resistance that could offset the benefits of using a higher conductivity substrate and lead to faster thermally enhanced degradation. The analysis reveals the importance using high-resolution imaging to detect hotspots and areas of peak temperature that largely affect failure initiation and device reliability and which may not be otherwise observable.

In this paper, electrical characterization results of N-polar GaN high-electron-mobility transistors that have been released from a 6H-SiC wafer and manually transferred to a Si wafer using a novel epitaxial lift-off (ELO) technique are presented. This recently developed ELO method uses a thin sacrificial layer of Nb2N, a hexagonal epitaxial conductor with less than 1% lattice mismatch to 4H- and 6H-SiC, to serve as the template for III-N device heterostructure growth. Measured results of transferred devices indicate that electron transport properties and low power density electrical performance are nominally unchanged relative to values measured before release. This technique has several advantages over competing ELO techniques, such as the well-known smart cut method, including bonding-ready released material with atomically-smooth backsides (≤ 0.5 nm rms), easy substrate reclaim with indefinite recycling potential, and a transfer process that can be performed after full front-side device processing and yield screening has been completed.

The activation of ion implanted p-type dopants in GaN is notoriously difficult as the extremely high temperatures required to activate implanted Mg also damage the GaN crystal. In this paper, we present refinements to our novel annealing process (symmetric multicycle rapid thermal annealing) to reduce surface damage and contamination responsible for elevated leakage currents and non-ideal diode behavior. Furthermore, we apply the technique to Mg-implanted bulk GaN substrates to enable vertical power device structures, demonstrating rectifying p-i-n junctions. In addition, the technique was applied for edge termination in both p-i-n and Schottky barrier diodes, realizing floating guard ring and junction termination extension structures. The processes demonstrated here represents a key enabling step for future GaN-based power devices.