This paper describes an innovative design automation tool, LAYGEN II, for analog integrated circuit (IC) layout generation based on template descriptions and on evolutionary computation techniques. LAYGEN II was developed giving special emphasis to the reusability of expert knowledge and to the efficiency of retargeting operations. The designer specifies the sized circuit-level structure, the required technology and also, the layout template consisting of technology and specification independent high-level layout guidelines. For placement, the topological relations present in the template are extracted to a nonslicing B*-tree layout representation, and the tool automatically merges devices and improves the floorplan quality. For routing an optimization kernel consisting of a tailored version of the multiobjective multiconstraint evolutionary algorithm NSGA-II is used. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic layout generation is demonstrated here using the LAYGEN II tool for typical analog circuit structures, and the results in GDSII format were validated using the industrial grade verification tool Calibre®.

In this paper, deep learning and artificial neural networks (ANNs) are used to size analog integrated circuits. In classical optimization-based sizing strategies the computational intelligent techniques are used to iterate over the map from devices sizes to circuits' performances, provided by design equations or circuit simulations, whereas here, it is performed an exploratory work on how ANNs can be capable of solving analog integrated circuit sizing as a direct map from specifications to the sizing. The proposed methodology was implemented and tested on a real circuit topology, with promising results. Moreover, trained ANNs were able to extend the circuit performance boundaries outside the train/validation set, showing that more than a mapping for the training data, the model is capable of learning reusable design patterns and provide promising designs.

Routing techniques for analog and radio-frequency (A/RF) integrated circuit (IC) design automation have been proposed in the literature for over three decades. On those, an extensive set of geometric constraints have already been covered as surrogates for routing quality, but also, performance-related criteria were progressively included. However, as A/RF design moved into advanced integration technology nodes, the increasing number of design rules/constraints, wire resistance, congestion, and interwire parasitic growth is constantly challenging existing automatic routing techniques and keeping pressure on their improvement. Fortunately, recent developments in modern workstations’ capabilities allowed the growth of sophisticated routing processes, including some assisted by the latest machine and deep learning methods, offering unprecedented solutions for the automation of this task. Still, as the correlation between routing-induced parasitic structures and the circuit’s functional behavior is far from simple, computational-intensive parasitic-inclusive and layout-aware synthesis techniques have also been proposed, where automatic routing techniques play a decisive role. This paper conducts an extensive review of A/RF IC routing techniques, from the digitally-inspired earliest approaches to state-of-the-art developments, providing a complete and comprehensive guide for circuit designers and design automation developers while defining research lines to facilitate more activities within this field.

In this paper, the use of machine learning techniques to repurpose already available Pareto optimal fronts of analog integrated circuit blocks for new contexts (loads, supply voltage, etc.) is explored. Data from previously sized circuits is used to train models that predict both circuit performance under the new context and the corresponding device sizes. A two-model chain is proposed, where, in the first layer, a multivariate polynomial regression estimates the performance tradeoffs. The output of this performance model is then used as input of an artificial neural network that predicts the device sizing that corresponds to that performance. Moreover, the models are trained with optimized sizing solutions, leading almost instantly to predicted solutions that are near optimal for the new context. The proposed methodology was integrated into a new framework and tested against a real circuit topology, with promising results. The model was able to predict wider and, in some cases, better, performance tradeoff, when compared to independent optimization runs for the same context, despite requiring 400 times fewer circuit simulations.