In this paper, deep learning and artificial neural networks (ANNs) are used to size analog integrated circuits. In classical optimization-based sizing strategies the computational intelligent techniques are used to iterate over the map from devices sizes to circuits' performances, provided by design equations or circuit simulations, whereas here, it is performed an exploratory work on how ANNs can be capable of solving analog integrated circuit sizing as a direct map from specifications to the sizing. The proposed methodology was implemented and tested on a real circuit topology, with promising results. Moreover, trained ANNs were able to extend the circuit performance boundaries outside the train/validation set, showing that more than a mapping for the training data, the model is capable of learning reusable design patterns and provide promising designs.

In this paper, the use of machine learning techniques to repurpose already available Pareto optimal fronts of analog integrated circuit blocks for new contexts (loads, supply voltage, etc.) is explored. Data from previously sized circuits is used to train models that predict both circuit performance under the new context and the corresponding device sizes. A two-model chain is proposed, where, in the first layer, a multivariate polynomial regression estimates the performance tradeoffs. The output of this performance model is then used as input of an artificial neural network that predicts the device sizing that corresponds to that performance. Moreover, the models are trained with optimized sizing solutions, leading almost instantly to predicted solutions that are near optimal for the new context. The proposed methodology was integrated into a new framework and tested against a real circuit topology, with promising results. The model was able to predict wider and, in some cases, better, performance tradeoff, when compared to independent optimization runs for the same context, despite requiring 400 times fewer circuit simulations.

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid non-systematic iterations between sizing and layout design steps, a multi-objective optimization-based layout-aware sizing approach with pre-optimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multi-net router with pre-optimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely-used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

This paper presents FUZYE, a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy c-means (FCM) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems, and, the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a k-means based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy.