The bandwidth-enhanced oversampling successive approximation (BE-OSA) readout technique is proposed in this article to reduce the noise floor of the readout circuit for micro-electromechanical systems (MEMS) capacitive accelerometer while achieving high power efficiency in terms of the figure of merit (FoM). The open-loop structure has been widely used in MEMS capacitive accelerometer for the Internet of Things (IoT) applications due to its low power consumption. However, in the open-loop accelerometer, the capacitance variation in the sensing element is limited to the femto-farad level to overcome nonlinearity. As a result, the thermal noise from the parasitic capacitance becomes significant. The ability of the readout circuit to deal with thermal noise is determined by the front-end switched-capacitor capacitance-to-voltage convertor (SC CVC) rather than the back-end analog-to-digital converter (ADC). To reduce the noise floor, the traditional oversampling method increases the sampling frequency of SC CVC by increasing the transconductance of the amplifier, but this leads to low power efficiency. In this work, the BE-OSA technique provides a high power efficiency method as it increases the sampling frequency of SC CVC without increasing the transconductance of the amplifier. The SC CVC based on the BE-OSA technique is demonstrated in a readout circuit fabricated by a commercial 0.18-μm BCD process and tested with a femto-farad MEMS accelerometer. The measurement results show that compared with the readout circuit without using the BE-OSA technique, the readout circuit using BE-OSA reduces the noise floor from 2.5 to 0.9 aF/√ Hz. Compared with other similar works, the proposed readout circuit achieves the best power efficiency in terms of both the absolute power efficiency (FoM₂ = 243 fJ) among the switched-capacitor readout circuits and the relative power efficiency (FoM₃ = 0.14).

This paper proposed an oversampling successive approximation (OSSA) technique to build switched-capacitor capacitance-to-voltage convertor (SC-CVC) for readout circuit of MEMS differential capacitive sensor. The readout circuit employing the OSSA technique has significantly improved resistance to common-mode parasitic capacitance of the input terminal of the readout circuit. In the OSSA readout circuit, there are five main non-ideal characteristics: holding error, recovery degradation, increment degradation, rise-edge degradation, and charge injection which reduce the accuracy and the settling time of the circuit. These problems are explained in detail and their solutions are given in this paper. The OSSA readout circuit is fabricated in a commercial 0.18-μm BCD process. To show the improvement evidently, a reported traditional readout circuit is also reproduced and fabricated using the same process. Compared with the traditional readout circuit, the proposed readout circuit reduces the effect of common-mode parasitic capacitance on the accuracy of SC-CVC by more than 23.8 dB, power dissipation by 69.3%, and die area by 50%.

Considering the propagation delay, dVSW/dt immunity, and power dissipation issues in bootstrapped high-side gate driver design, a monolithic high-voltage DC-DC buck converter with high-speed dynamic level shifter and improved gate drive buffer is presented in this paper. With the introduction of an instantaneous dynamic current, the propagation delay of the level shifter is reduced to 1.13 ns for the high-side switch. The dVSW/dt immunity is enhanced by a dynamic current compensation during positive slewing and a diode voltage clamp during negative slewing. The average current consumption of the level shifter is only 8.45 μA at a switching frequency of 1 MHz. The proposed gate drive buffer eliminates the shoot-through current with the use of dead time control. The compact level shifter and buffer are also used to drive an integrated p-MOS transistor serving as a bootstrap diode emulator. Experimental results show that the fabricated converter with the proposed scheme regulates well with an 18 V input, 1.05 V output and 2 A load current. Also, high efficiency of up to 93 % is achieved.

To achieve high frequency and high efficiency over a wide load range, a monolithic voltage-mode DC-DC buck converter with advanced burst mode (ABM) and pulse width modulation (PWM) is presented in this paper. The load current is detected by estimating the currents flowing through the high side and low side switches, which maintains a near constant mode changing point. A counter-based scheme is used to achieve seamless and smooth transition between PWM and ABM. Both operating modes share the same control blocks and no additional zero current detecting circuit is needed. In addition, the output stage switch size can be adjusted to reduce switching loss and improve efficiency under ultra-light load conditions. Experimental results show that the integrated 3 MHz converter achieves high efficiency from 80 to 91 %, over a wide load range, from 0.001 to 5 A. When the switch size is set to 1/3 of the maximum value, an additional 5 % efficiency improvement at under 0.1 A load can be realized. The mode changing point is set at 0.4 A with less than 10 % variation when the input voltage changes from 3 to 5 V. The load transient response is also improved significantly.

In the electrical power system, the coordination of directional overcurrent protection relays (DOPR) plays a preeminent role in protecting the electrical power system with the help of primary and back up protection to keep the system vigorous and to avoid unnecessary interruption. The coordination between these relays should be pursued at optimal value to minimize the total operating time of all main relays. The coordination of directional overcurrent relay is a highly constrained optimization problem. The DOPR problem has been solved by using a hybridized version of particle swarm optimization (HPSO). The hybridization is achieved by introducing simulated annealing (SA) in original PSO to avoid being trapped in local optima and successfully searching for a global optimum solution. The HPSO has been successfully applied to five case studies. Furthermore, the obtained results outperform the other traditional and state of the art techniques in terms of minimizing the total operating of DOPR and convergence characteristics, and require less computational time to achieve the global optimum solution.

Two issues plaguing the on-time control dc–dc buck converter are the system instability caused by low equivalent series resistance (ESR) output capacitor and the great variation on switching frequency caused by input/output voltage and load current. Without additional external components or integrated clock-controlled circuits and RC filters, the reference and frequency compensation (RFC) technique is presented in this article to stabilize the converter and eliminate its switching frequency variation issue with a low ESR output capacitor. The proposed frequency-stable on-time control buck converter with input voltage ranging from 4.5 to 30 V and output load ranging up to 6 A was fabricated using a standard 0.25- μ m BCD (BiCMOS/DMOS) process. With a low ESR ceramic output capacitor, the experimental results show that the converter functions properly and stably over the whole load range, and the switching frequency variation with load current is constrained to 3.8 kHz/A, which is a fairly constant value. Moreover, the peak efficiency of the converter is about 98% and the load transient response is also shown excellent performance with the load stepping from 0.1 to 6 A.