Conventional di/dt and dv/dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

With ever-increasing demand of feature-rich portable electronics, single-inductor multiple-output (SIMO) converters are becoming a cost-effective option to provide different supply voltages while maintaining a long battery life. A single-discharge (SDC) control scheme is proposed to simplify the SIMO design, to achieve low cross-regulation, and to support wide range of loads with reasonable power efficiency. A SDC SIMO buck converter with four outputs composed of comparators, phased-locked loop, finite state machine (FSM) controller, and an output stage, is prototyped using TSMC's 0.18-μm BCD process. In addition to the basic switching functions, the FSM controller provides a state skipping feature to allow no-load regulation. Its functionality is verified experimentally and can convert an input voltage from 2.7 to 3.7 V to 1, 1.2, 1.5, and 1.8 V outputs. The simulated peak power conversion efficiency is 86% with a combined output power ranging from 150 to 300 mW. The packaged SDC SIMO converter ICs exhibit a lower measured peak efficiency of 73%, with a cross-regulation of 0.24 mV/mA due to the parasitic bond-wire resistance. The converter prototype can support a wide range of loading conditions, from open circuit to a total output power of 1 W.

This paper presents a new Insulated Gate Bipolar Transistor (IGBT) over-current detection method based on the analysis of the gate voltage. IGBT gate voltage turn-on transient pattern is analyzed for the detection of IGBT Hard Switching Fault (HSF). On-state gate voltage is monitored to detect IGBT Fault Under Load (FUL). IGBT turn-off Miller plateau voltage is extracted and measured to sense the IGBT collector current in case of over-load condition. Compared to the commonly used IGBT short circuit detection methods or collector current sensing methods, this method can provide indirect fast detection of IGBT short circuit and accurate measurement of over-load within one switching period. The feasibility and effectiveness of the proposed approach are validated both by simulation and experimental results. Measurement results show that HSF and FUL can be detected within 0.6 μs and 0.5 μs, respectively. By comparing the extracted plateau voltage (VPL) with a preset reference voltage (VOCx), the IGBT over-load can be detected with a maximum deviation of ±1.2 A when IC ranges from 3 to 110 A.

Considering the propagation delay, dVSW/dt immunity, and power dissipation issues in bootstrapped high-side gate driver design, a monolithic high-voltage DC-DC buck converter with high-speed dynamic level shifter and improved gate drive buffer is presented in this paper. With the introduction of an instantaneous dynamic current, the propagation delay of the level shifter is reduced to 1.13 ns for the high-side switch. The dVSW/dt immunity is enhanced by a dynamic current compensation during positive slewing and a diode voltage clamp during negative slewing. The average current consumption of the level shifter is only 8.45 μA at a switching frequency of 1 MHz. The proposed gate drive buffer eliminates the shoot-through current with the use of dead time control. The compact level shifter and buffer are also used to drive an integrated p-MOS transistor serving as a bootstrap diode emulator. Experimental results show that the fabricated converter with the proposed scheme regulates well with an 18 V input, 1.05 V output and 2 A load current. Also, high efficiency of up to 93 % is achieved.

To achieve high frequency and high efficiency over a wide load range, a monolithic voltage-mode DC-DC buck converter with advanced burst mode (ABM) and pulse width modulation (PWM) is presented in this paper. The load current is detected by estimating the currents flowing through the high side and low side switches, which maintains a near constant mode changing point. A counter-based scheme is used to achieve seamless and smooth transition between PWM and ABM. Both operating modes share the same control blocks and no additional zero current detecting circuit is needed. In addition, the output stage switch size can be adjusted to reduce switching loss and improve efficiency under ultra-light load conditions. Experimental results show that the integrated 3 MHz converter achieves high efficiency from 80 to 91 %, over a wide load range, from 0.001 to 5 A. When the switch size is set to 1/3 of the maximum value, an additional 5 % efficiency improvement at under 0.1 A load can be realized. The mode changing point is set at 0.4 A with less than 10 % variation when the input voltage changes from 3 to 5 V. The load transient response is also improved significantly.

Conventional IGBT current sensing and protection techniques usually employ discrete sensors such as lossy shunt resistors and may involve accessing the high voltage collector load of the IGBT. This would normally present difficulties for integration. This paper presents an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for local data processing. This IC is prototyped using TSMC 0.18 μm 40 V BCD Gen-2 process. The collector current sensing technique is based on the unique Miller plateau relationship between the gate current and collector current (IC and IG) for a particular gate resistance (RG). It allows a cycle by cycle measurement of IC during both turn-on and turn-off transients without any extra discrete components. The temperature variation is compensated internally by the on-chip CPU using polynomial curve fitting. This technique only monitors the low voltage signal at the gate terminal, without the need to handle any high voltage signal on the collector/load side. Measurements using a double pulse test setup show an accuracy of ±0.5 A over the current ranges between 1 to 30 A for turn-on and 1 to 50 A for turn-off from 25oC to 75oC.