Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is based on the fact that dimension-ordered routing algorithms imposes the highest traffic load on the central nodes in mesh topologies. To balance the traffic over the network, certain routers at the east and the west of NoC, with dimension-order XY routing, statically are configured as YX. Various configurations have been explored for LAXY and the simulations show a specific configuration, called Fishtail, increases mean time to failure of the routers and interconnects by about 42% and 56%, respectively. Moreover, by balancing the load over the network, LAXY improves overall packet latency by about 7% in average, with negligible area overhead.

Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about 2.7x of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging sensors. Furthermore, the presented sensor can detect and correct half of the Single Event Upsets (SEUs), which lead to a bit-flip in the flip-flop. In addition, by utilizing the SEU detection circuitry, a scheme for reducing Bias Temperature Instability (BTI), the most important aging process in the memory structures, is presented by balancing the duty cycle of the flip-flop transistors with negligible extra overhead.

Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on TSVs. The severity of TSV-to-TSV crosstalk faults depend on the transition patterns appearing on the TSVs. To reduce the crosstalk faults in TSVs, this paper intends to propose Fibonacci-based 3D-Crosstalk Avoidance Code (3D-CAC) called 3D-Doubled Penultimate Summation-based (3D-DPS) CAC. 3D-DPS can completely omit 3D-Tripple opposite Direction Transition (3D-TOD) and is applicable to any arbitrary width of 3×N TSV mesh. 3D-DPS has not ambiguity in representing code words and generates unique code word for each data word. In addition, 3D-DPS considers overlaps between transitions of 3×N TSV meshs by using a mechanism called Coding Window. Evaluation results show that 3D-DPS reduces the area occupation, power consumption and critical path of codec by 53.0%, 25.2% and 1.5%, respectively in comparison with state-of-the-art 3D-CAC.

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

Embedded systems have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-core processors, which are commonly used to design MC systems, bring out new challenges due to the process variations. Power and frequency asymmetry affects the predictability of embedded systems. In this work, variation-aware techniques are explored to not only improve the reliability of MC systems, but also aid the scheduling and energy saving of them. We leverage the core-to-core (C2C) variations to protect high-criticality tasks and provide full service for a high percentage of low-criticality tasks. We formulate a constrained Integer Linear Program (ILP) and propose an optimization heuristic for task mapping and scheduling under Process Variation in Mixed-Criticality systems (PVMC). Our proposed techniques also guarantee timing, reliability, and Thermal Design Power (TDP) constraints by considering the impact of task mapping in variation-affected platforms on system reliability and peak power consumption. Experiments demonstrate that our ILP framework and PVMC algorithm can greatly improve the schedulability and the overall Quality-of-Service (QoS), and provide energy saving up to 27.1% under different quantities of process variation compared with a state-of-the-art algorithm.